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MC56F8322/D Rev. 3.0 10/2003
56F8322
Preliminary Technical Data
56F8322 16-bit Hybrid Controller
* Up to 60 MIPS at 60MHz core frequency * DSP and MCU functionality in a unified, C-efficient architecture * 32KB Program Flash * 4KB Program RAM * 8KB Data Flash * 8KB Data RAM * 8KB Boot Flash * One 6-channel PWM Module * Two 3-channel 12-bit ADCs * Temperature Sensor
RESET 4 6
* One Quadrature Decoder * FlexCAN Module * Up to two Serial Communication Interfaces (SCIs) * Up to two Serial Peripheral Interfaces (SPIs) * Two General Purpose Quad Timers * Computer Operating Properly (COP)/Watchdog * On-Chip Relaxation Oscillator * JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging * Up to 21 GPIO lines * 48-pin LQFP Package
VCAP 2 VDD 4 4
Digital Reg Analog Reg
VSS
VDDA
VSSA
PWM Outputs Fault Inputs
PWMA or SPI1 or GPIOA
Program Controller and Hardware Looping Unit
JTAG/ EOnCE Port
16-Bit 56800E Core
Low Voltage Supervisor Bit Manipulation Unit
Address Generation Unit
Data ALU 16 x 16 + 36 AE 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators
3 3 3
AD0 AD1
VREF Temp_Sense
PAB PDB CDBR CDBW
Memory
Program Memory 16K x 16 Flash 2K x 16 RAM 4K x 16 Boot Flash Data Memory 4K x 16 Flash 4K x 16 RAM
XDB2 XAB1 XAB2 PAB PDB CDBR CDBW
R/W Control
System Bus Control
4
Quadrature Decoder 0 or Quad Timer A
IPBus Bridge (IPBB)
2 Quad Timer C or SCI0 or GPIOC FlexCAN or GPIOC Peripheral Device Selects RW Control IPWDB IPRDB
2
Decoding Peripherals
Clock resets
PLL
SPI0 or SCI1 or GPIOB 4
COP/ Watchdog
Interrupt Controller
System P O Integration R Module
O Clock S Generator* C
XTAL or GPIOC EXTAL or GPIOC
IRQA
*Includes On-Chip Relaxation Oscillator
56F8322 Block Diagram
(c) Motorola, Inc., 2003. All rights reserved.
56F8322 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . 3
1.1. 56F8322 Features . . . . . . . . . . . . . . . . . . 3 1.2. 56F8322 Description . . . . . . . . . . . . . . . . 4 1.3. Award-Winning Development Environment . . . . . . . . . . . . . . . 5 1.4. Architecture Block Diagram . . . . . . . . . . 5 1.5. Product Documentation . . . . . . . . . . . . . 8 1.6. Data Sheet Conventions . . . . . . . . . . . . . 9
Part 7: Security Features . . . . . . . . . . . . . 84
7.1. Operation with Security Enabled . . . . . .84 7.2. Flash Access Blocking Mechanisms. . . 84
Part 8: General Purpose Input/Output (GPIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.1. Introduction. . . . . . . . . . . . . . . . . . . . . . 86 8.2. Configuration . . . . . . . . . . . . . . . . . . . . 86 8.3. Memory Maps . . . . . . . . . . . . . . . . . . . .88
Part 2: Signal/Connection Descriptions 10
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . 10 2.2. 56F8322 Signal Pins . . . . . . . . . . . . . . . 12
Part 9: Joint Test Action Group (JTAG) 88
9.1. 56F8322 Information . . . . . . . . . . . . . . 88
Part 3: On-Chip Clock Synthesis (OCCS) 19
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 19 3.2. External Clock Operation. . . . . . . . . . . 19 3.3. Use of On-Chip Relaxation Oscillator . 20 3.4. Internal Clock Operation . . . . . . . . . . . 21 3.5. Registers . . . . . . . . . . . . . . . . . . . . . . . . 22
Part 10: Specifications . . . . . . . . . . . . . . . 89
10.1. General Characteristics . . . . . . . . . . . . 89 10.2. DC Electrical Characteristics . . . . . . . .94 10.3. AC Electrical Characteristics . . . . . . . 97 10.4. Flash Memory Characteristics . . . . . . .98 10.5. External Clock Operation Timing . . . .98 10.6. Phase Locked Loop Timing . . . . . . . . 99 10.7. Oscillator Parameters . . . . . . . . . . . . .100 10.8. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . . . .101 10.9. Serial Peripheral Interface (SPI) Timing 103 10.10. Quad Timer Timing . . . . . . . . . . . . 106 10.11. Quadrature Decoder Timing . . . . . .106 10.12. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . . .107 10.13. Controller Area Network (CAN) Timing . . . . . . . . . . . .108 10.14. JTAG Timing . . . . . . . . . . . . . . . . . .108 10.15. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . . . .110 10.16. Equivalent Circuit for ADC Inputs .111 10.17. Power Consumption . . . . . . . . . . . . 111
Part 4: Memory Map . . . . . . . . . . . . . . . . 23
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . 23 4.2. Program Map . . . . . . . . . . . . . . . . . . . . 23 4.3. Interrupt Vector Table . . . . . . . . . . . . . 24 4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5. Flash Memory Map . . . . . . . . . . . . . . . . 26 4.6. EOnCE Memory Map . . . . . . . . . . . . . . 28 4.7. Peripheral Memory Mapped Registers . 28
Part 5: Interrupt Controller (ITCN) . . . 44
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . 44 5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3. Functional Description . . . . . . . . . . . . . 44 5.4. Block Diagram . . . . . . . . . . . . . . . . . . . 46 5.5. Operating Modes . . . . . . . . . . . . . . . . . 46 5.6. Register Descriptions . . . . . . . . . . . . . . 47 5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Part 11: Packaging . . . . . . . . . . . . . . . . . 113
11.1. Package and Pin-Out Information 56F8322 . . . . . . . . . . . . . . . . .113
Part 6: System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . 69
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . 69 6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3. Operating Modes . . . . . . . . . . . . . . . . . 69 6.4. Operating Mode Register . . . . . . . . . . . 70 6.5. Register Descriptions . . . . . . . . . . . . . . 71 6.6. Clock Generation Overview . . . . . . . . . 82 6.7. Power-Down Modes. . . . . . . . . . . . . . . 82 6.8. Stop and Wait Mode Disable Function 83 6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Part 12: Design Considerations . . . . . . . 116
12.1. Thermal Design Considerations . . . . 116 12.2. Electrical Design Considerations . . . .117 12.3. Power Distribution and I/O Ring Implementation . . . . . . . . . . .118
Part 13: Ordering Information . . . . . . . 119
Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.
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56F8322 Technical Data Preliminary
MOTOROLA
56F8322 Features
Part 1 Overview
1.1 56F8322 Features
1.1.1
* * * * * * * * * * * * * *
Hybrid Controller Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture As many as 60 Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators including extension bits Arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/EOnCE debug programming interface
1.1.2
* * *
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection On-chip memory including a low-cost, high-volume Flash solution -- 32KB of Program Flash -- 4KB of Program RAM -- 8KB of Data Flash -- 8KB of Data RAM -- 8KB of Boot Flash
*
EEPROM emulation capability
1.1.3
* *
Peripheral Circuits for 56F8322
One Pulse Width Modulator module with six PWM outputs, and one Fault input, fault-tolerant design with dead time insertion; supports both center- and edge-aligned modes Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with dual, 3-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, Channel 2 Temperature Sensor is tied internally to analog input (ANA7) to monitor the on-chip temperature Two 16-bit Quad Timer modules (TMR) totaling six pins: Timer A works in conjunction with Quad Decoder 0 and Timer C works in conjunction with the PWMA and ADCA One Quadature Decoder which works in conjunction with Quad Timer A FlexCAN (Can Version 2.0 B-compliant) Module with 2-pin port for transmit and receive Up to two Serial Communication Interfaces (SCIs)
56F8322 Technical Data Preliminary 3
* * * * *
MOTOROLA
* * * * * * * *
Up to two Serial Peripheral Interfaces (SPIs)
Computer-Operating Properly (COP)/Watchdog timer One dedicated external interrupt pin 21 General Purpose I/O (GPIO) pins Integrated Power-On Reset and Low-Voltage Interrupt Module JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, processor speed-independent, real-time debugging Software-programmable, Phase Lock Loop (PLL) On-chip relaxation oscillator
1.1.4
* * * * * *
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power
1.2 56F8322 Description
The 56F8322 is a member of the 56800E core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8322 is well-suited for many applications. The 56F8322 includes many peripherals that are especially useful for applications such as automotive control; industrial control and networking; motion control; home appliances; general purpose inverters; smart sensors; fire and security systems; power management; and medical monitoring. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers to enable rapid development of optimized control applications. The 56F8322 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8322 also provides one external dedicated interrupt line and up to 21 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F8322 hybrid controller includes 32KB of Program Flash and 8KB of Data Flash, each programmable through the JTAG port, and 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F8322 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and is also capable of supporting six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead-time insertion, distortion correction
4 56F8322 Technical Data Preliminary MOTOROLA
Award-Winning Development Environment
via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A "smoke-inhibit", write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1/2 (center-aligned mode only) to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters (ADCs) through Quad Timer C, channel 2. The 56F8322 incorporates one Quadrature Decoder capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a timeout value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This hybrid controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), two Quad Timers and FlexCAN. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIOs) if that function is not required. A Flex Controller Area Network interface (CAN Version 2.0 A/B-compliant) and an internal interrupt controller are also a part of the 56F8322.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8322's architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IP Bus Bridge. Table 1-1 lists the internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2 shows the peripherals and control blocks connected to the IP Bus Bridge. The figures do not show the on-board regulator and power and ground signals. They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Part 2 Signal/Connection Descriptions to see which signals are multiplexed with those of other peripherals. Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer C input channel as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals.
MOTOROLA
56F8322 Technical Data Preliminary
5
4 JTAG / EOnCE
Boot Flash pdb_m[15:0] pab[20:0] Program Flash Program RAM
cdbw[31:0]
56800E
CHIP TAP Controller
TAP Linking Module
xab1[23:0] xab2[23:0]
Data RAM
External JTAG Port cdbr_m[31:0] xdb2_m[15:0]
Data Flash
IP Bus Bridge
To Flash Control Logic
Flash Interface Unit(s) IP Bus
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Interface Unit (FIU). Flash control is accomplished by the I/O to the FIU over the peripheral bus, while reads and writes are completed between the core and the Flash memories. The primary data RAM port is 32 bits wide. Other data ports are16 bits.
56F8322 Technical Data Preliminary MOTOROLA
Note:
6
Architecture Block Diagram
To/From IP Bus Bridge
CLKGEN (OSC/PLL)
Interrupt Controller
(ROSC) Low Voltage Interrupt Timer A
POR & LVI
4
Quadrature Decoder 0
System POR
SIM
RESETB
COP Reset 2 FlexCAN COP SPI 1 4 SPI 0 PWM A 3 SYNC Output 2
4
2
SCI 1
GPIO A GPIO B GPIO C
SCI 0
ch2i
2
Timer C
ch2o
ADC A Temp. Sense
6
IP Bus
The dotted line on Temp. Sense signifies the Pad-to-Pad bond between TEMP_SENS and ANA7 on the 56F8322.
Figure 1-2 Peripheral Subsystem
MOTOROLA
56F8322 Technical Data Preliminary
7
Table 1-1 Bus Signal Names
Name
pdb_m[15:0] cdbw[15:0] pab[20:0] cdbr_m[31:0] cdbw[31:0] xab1[23:0]
Function Program Memory Interface
Program data bus for instruction word fetches or read operations. Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
Primary core data bus for memory reads. Addressed via xab1 bus. Primary core data bus for memory writes. Addressed via xab1 bus. Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written on cdbw and returned on cdbr_m. Also used to access memory mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0] xab2[23:0] Secondary data bus used for Secondary data address bus xab2 in the dual memory reads. Secondary data address bus used for the second of two simultaneous accesses. Capable of addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0] Peripheral Bus accesses all On-Chip peripherals registers. This bus operates at the same clock rate as the Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.
1.5 Product Documentation
The four documents listed in Table 1-2 are required for a complete description and proper design with the 56F8322. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at http://www.motorola.com/semiconductors/.
Table 1-2 56F8322 Chip Documentation
Topic DSP56800E Reference Manual 56F8300 Peripheral User Manual 56F8322 Technical Data Sheet 56F8322 Product Brief 56F8322 Errata Description Detailed description of the 56800E family architecture, 16-bit hybrid controller core processor, and the instruction set Detailed description of peripherals of the 56F8300 family of devices Electrical and timing specifications, pin descriptions, and package descriptions (this document) Summary description and block diagram of the 56F8322 core, memory, peripherals and interfaces Details any chip issues that might be present Order Number DSP56800ERM/D
MC56F8300UM/D MC56F8322/D MC56F8322PB/D MC56F8322E/D
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56F8322 Technical Data Preliminary
MOTOROLA
Data Sheet Conventions
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
"asserted" "deasserted" Examples:
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
MOTOROLA
56F8322 Technical Data Preliminary
9
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8322 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group Power (VDD or VDDA) Ground (VSS or VSSA) Supply Capacitors & VPP1 PLL and Clock Interrupt and Program Control Pulse Width Modulator (PWM) Ports2 Serial Peripheral Interface (SPI) Port 03 Quadrature Decoder Port 04 CAN Ports Analog to Digital Converter (ADC) Ports Timer Module Port C5 JTAG/Enhanced On-Chip Emulation (EOnCE) Temperature Sensor6 Number of Pins 5 5 2 2 2 7 4 4 2 9 2 4 0
1. The VPP input shares the IRQA input 2. Pins in this section can function as SPI #1 and GPIO. 3. Pins in this section can function as SCI #1 and GPIO. 4. Alternately, can function as Quad Timer A pins or GPIO. 5. Pins can function as SCI #0 and GPIO. 6. Tied internally to ANA7
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56F8322 Technical Data Preliminary
MOTOROLA
Introduction
Power Ground Power Ground
VDD_IO
VSS VDDA_ADC VSSA_ADC
4 4 1 1
1 1 1 1
PHASEA0 (TA0, GPIOB7) PHASEB0 (TA1, GPIOB6) INDEX0 (TA2, GPIOB5) HOME0 (TA3, GPIOB4) SCLK0 (GPIOB3) MOSI0 (GPIOB2) MISO0 (RXD1, GPIOB1) SS0 (TXD1, GPIOB0) PWMA0 -1 (GPIOA0 - 1) PWMA2 (SS1, GPIOA2) PWMA3 (MISO1, GPIOA3) PWMA4 (MOSI1, GPIOA4) PWMA5 (SCLK1, GPIOA5) FAULTA0 (GPIOA6) PWMA or SPI1 or GPIO SPI0 or SCI1 or GPIO Quadrature Decoder 0 or Quad Timer A or GPIO
56F8322
Other Supply Ports VCAP1 - VCAP2 2
1 1
PLL and Clock or GPIO
EXTAL (GPIOC0) XTAL (GPIOC1)
1 1 1 2 1 1 1 1 1 1
3 3 3
ANA0 - 2 ANA4 - 6 VREF ADCA
1 1
CAN_RX (GPIOC2) CAN_TX (GPIOC3)
FlexCAN or GPIO
TCK JTAG/ EOnCE Port TMS TDI TDO
1 1 1 1
1 1
TC0 (TXD0, GPIOC6) TC1 (RXD0, GPIOC5) IRQA (VPP) RESET
QUAD TIMER or SCI0 or GPIO INTERRUPT/ PROGRAM CONTROL
1 1
Figure 2-1 56F8322 Signals Identified by Functional Group (48-Pin LQFP)
MOTOROLA
56F8322 Technical Data Preliminary
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2.2 56F8322 Signal Pins
After reset, all pins are by default the primary function. Any alternate functionality must be programmed.
Table 2-2 56F8322 Signal and Package Information for the 48 Pin LQFP
Signal Name VDD_IO VDD_IO VDD_IO VDD_IO VDDA_ADC Pin No. 5 14 34 44 30 Supply ADC Power -- This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. Ground -- These pins provide ground for chip logic and I/O drivers. Type Supply State During Reset Signal Description I/O Power -- This pin supplies 3.3V power to the chip I/O interface.
VSS VSS VSS VSS VSSA_ADC
10 13 31 45 29
Supply
Supply
ADC Analog Ground -- This pin supplies an analog ground to the ADC modules. Supply VCAP1 - 2 -- Connect each pin to a 2.2F or bigger bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. External Crystal Oscillator Input -- This input can be connected to an 8MHz external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to VSS. The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL.
VCAP1 VCAP2 EXTAL
43 17 32
Supply
Input/
Input
(GPIOC0)
Schmitt Input/ Output
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is an EXTAL input with pull-ups disabled.
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56F8322 Technical Data Preliminary
MOTOROLA
56F8322 Signal Pins
Table 2-2 56F8322 Signal and Package Information for the 48 Pin LQFP
Signal Name XTAL Pin No. 33 Type Output State During Reset Output Signal Description Crystal Oscillator Output -- This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to VSS. The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL. (GPIOC1) Schmitt Input/ Output Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is an XTAL input with pull-ups disabled. TCK 39 Schmitt Input Input, pulled Test Clock Input -- This input pin provides a gated clock to low internally synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-down resistor. A Schmitt trigger input is used for noise immunity. Input, pulled Test Mode Select Input -- This input pin is used to high sequence the JTAG TAP controller's state machine. It is internally sampled on the rising edge of TCK and has an on-chip pull-up resistor. Input, pulled Test Data Input -- This input pin provides a serial input data high stream to the JTAG/EOnCE port. It is sampled on the rising internally edge of TCK and has an on-chip pull-up resistor. Tri-stated Test Data Output -- This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Phase A -- Quadrature Decoder 0 PHASEA input
TMS
40
Schmitt Input
TDI
41
Schmitt Input
TDO
42
Output
PHASEA0
38
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output Output
Input
(TA0)
TA0 -- Timer A Channel 0
(GPIOB7)
Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(oscillator_clock)
Clock Output - can be used to monitor the internal oscillator clock signal (see Section 6.5.7 CLKO Select Register (SIM_CLKOSR). After reset, the default state is PHASEA0.
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56F8322 Technical Data Preliminary
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Table 2-2 56F8322 Signal and Package Information for the 48 Pin LQFP
Signal Name PHASEB0 Pin No. 37 Type Schmitt Input Schmitt Input/ Output Schmitt Input/ Output Output State During Reset Input Signal Description Phase B -- Quadrature Decoder 0 PHASEB input
(TA1)
TA1 -- Timer A Channel 1
(GPIOB6)
Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(sys_clk2x)
Clock Output - can be used to monitor the internal sys_clk2x signal (see Section 6.5.7 CLKO Select Register (SIM_CLKOSR). After reset, the default state is PHASEB0.
INDEX0
36
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output Output
Input
Index -- Quadrature Decoder 0 INDEX input
(TA2)
TA2 -- Timer A Channel 2
(GPIOB5)
Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(sys_clk)
Clock Output - can be used to monitor the internal sys_clk signal (see Section 6.5.7 CLKO Select Register (SIM_CLKOSR).
After reset, the default state is INDEX0. HOME0 35 Schmitt Input Schmitt Input/ Output Schmitt Input/ Output Output Input Home -- Quadrature Decoder 0 HOME input
(TA3)
TA3 -- Timer A Channel 3
(GPIOB4)
Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(prescaler_clock)
Clock Output - can be used to monitor the internal prescaler_clock signal (see Section 6.5.7 CLKO Select Register (SIM_CLKOSR).
After reset, the default state is HOME0.
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56F8322 Technical Data Preliminary
MOTOROLA
56F8322 Signal Pins
Table 2-2 56F8322 Signal and Package Information for the 48 Pin LQFP
Signal Name SCLK0 Pin No. 19 Type Schmitt Input/ Output State During Reset Tri-stated Signal Description SPI 0 Serial Clock -- In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCLK0. MOSI0 18 Schmitt Input/ Output Tri-stated SPI 0 Master Out/Slave In -- This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is MOSI0. Input SPI 0 Master In/Slave Out -- This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. Receive Data -- SCI1 receive data input (RXD1) Schmitt Input Schmitt Input/ Output 15 Schmitt Input Input Port B GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is MISO0. SPI 0 Slave Select -- SS0 is used in slave mode to indicate to the SPI module that the current transfer is to be received. Transmit Data -- SCI1 transmit data output (TXD1) Schmitt Output Schmitt Input/ Output Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SS0.
(GPIOB3)
Schmitt Input/ Output
(GPIOB2)
Schmitt Input/ Output 16 Schmitt Input/ Output
MISO0
(GPIOB1)
SS0
(GPIOB0)
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Table 2-2 56F8322 Signal and Package Information for the 48 Pin LQFP
Signal Name PWMA0 Pin No. 3 Type Schmitt Output Schmitt Input/ Output State During Reset Tri-stated Signal Description PWMA0 -- This is one of six PWMA output pins.
(GPIOA0)
Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PWMA0.
PWMA1
4
Schmitt Output Schmitt Input/ Output
Tri-stated
PWMA1 -- This is one of six PWMA output pins.
(GPIOA1)
Port A GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PWMA1.
PWMA2 (SS1)
6
Output Schmitt Input
Tri-stated
PWMA2 -- This is one of six PWMA output pins. SPI1 Slave Select -- SS1 is used in slave mode to indicate to the SPI module that the current transfer is to be received. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PWMA2.
(GPIOA2)
Schmitt Input/ Output
PWMA3 (MISO1)
7
Output Schmitt Input/ Output
Tri-stated
PWMA3 -- This is one of six PWMA output pins. SPI1 Master In/Slave Out -- This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PWMA3.
(GPIOA3)
Schmitt Input/ Output 8 Output Schmitt Input/ Output Tri-stated
PWMA4 (MOSI1)
PWMA4 -- This is one of six PWMA output pins. SPI1 Master Out/Slave In -- This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PWMA4.
(GPIOA4)
Schmitt Input/ Output
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56F8322 Signal Pins
Table 2-2 56F8322 Signal and Package Information for the 48 Pin LQFP
Signal Name PWMA5 (SCLK1) Pin No. 9 Type Output Schmitt Input/ Output State During Reset Tri-stated Signal Description PWMA5 -- This is one of six PWMA output pins. SPI 1 Serial Clock -- In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PWMA5. FAULTA0 12 Schmitt Input Input FAULTA0 -- This fault input pin is used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is FaultA0. ANA0 ANA1 ANA2 ANA4 ANA5 ANA6 VREFP VREFMID VREFN CAN_RX 20 21 22 23 24 25 28 27 26 46 Schmitt Input Schmitt Input/ Output Input FlexCAN Receive Data -- This is the CAN input. This pin has an internal pull-up resistor. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is CAN_RX. Input/ Output Input/ Output VREFP, VREFMID & VREFN -- Internal pins for voltage reference which are brought off-chip so that they can be bypassed. Connect to a 0.1 F low ESR capacitor. Input Input ANA0 - 2 and ANA4 - 6 -- Analog inputs to ADC A
(GPIOA5)
Schmitt Input/ Output
(GPIOA6)
Schmitt Input/ Output
(GPIOC2)
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Table 2-2 56F8322 Signal and Package Information for the 48 Pin LQFP
Signal Name CAN_TX (GPIOC3) Pin No. 47 Type Output Schmitt Input/ Output State During Reset Tri-stated Signal Description FlexCAN Transmit Data -- CAN output Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is CAN_TX. TC0 1 Schmitt Input/ Output Schmitt Input Schmitt Input/ Output Input TC0 -- Timer C Channel 0
(TXD0)
Transmit Data -- SCI0 transmit data output
(GPIOC6)
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC0.
TC1
48
Schmitt Input/ Output Output Schmitt Input/ Output
Input
TC1 -- Timer C Channel 1
(RXD0) (GPIOC5)
Receive Data -- SCI0 receive data input Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC1.
IRQA
11
Schmitt Input
Input
External Interrupt Request A -- The IRQA input is an asynchronous external interrupt request during stop and wait mode operation. During other operating modes, it is a synchronized external interrupt request, which indicates an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. VPP -- This pin is used for Flash debugging purposes.
(VPP) RESET 2 Schmitt Input Input Reset -- This input is a direct hardware reset on the processor. When RESET is asserted low, the hybrid controller is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks.
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Introduction
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the Peripheral Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design that apply to the 56F8322 part.
3.2 External Clock Operation
The 56F8322 system clock can be derived from an external crystal, ceramic resonator or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins.
3.2.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 10-16. A recommended crystal oscillator circuit is shown in Figure 3-1. Follow the crystal supplier's recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL XTAL Rz
CLKMODE = 0
EXTAL XTAL Rz
Sample External Crystal Parameters: Rz = 750 K Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg
CL1
CL2
Figure 3-1 Connecting to a Crystal Oscillator
Note: The OCCS_COHL bit should be set to 1 when a crystal oscillator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in Section 5 of the 56F8300 Peripheral User Manual.
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3.2.2
Ceramic Resonator (Default)
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-2. Refer to supplier's recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 2 Terminal 3 Terminal
EXTAL XTAL Rz
EXTAL XTAL Rz
Sample External Ceramic Resonator Parameters: Rz = 750 K
CL1
CL2
CLKMODE = 0
C1
C2
Figure 3-2 Connecting a Ceramic Resonator
Note: The OCCS_COHL bit is set to 0 when a crystal resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in Section 5 of the 56F8300 Peripheral User Manual.
3.2.3
External Clock Source
The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to XTAL and the EXTAL pin is grounded.
56F8322 XTAL EXTAL External Clock VSS or GPIO
Note: when using an external clocking source with this configuration, the CLKMODE and COHL bits of the OSCTL register should be set to 1.
Figure 3-3 Connecting an External Clock Signal
3.3 Use of On-Chip Relaxation Oscillator
An internal relaxtion oscillator can supply the reference frequency when an external frequency source of crystal are not used. During a 56F8322 boot or reset sequence, the relaxation oscillator is enabled by default, and the PRECS bit in the PLLCR word is set to 0. If an external oscillator is connected, the relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. If a changeover between internal and external oscillators is required at startup, internal device circuits compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not switched until the desired clock is enabled and stable.
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Internal Clock Operation
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.1% of 8MHz by trimming an internal capacitor. Bits 0-9 of the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset value to increase or decrease capacitance. Upon power-up, the default value of this trim is 512 units. Each unit added or deleted changes the output frequency by about 0.1%, allowing incremental adjustment until the desired frequency accuracy is achieved. The internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash information block and loaded to the FMIFROPT1 register at reset. For further information, see Section 6 in the 56F8300 Peripheral User Manual. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM.
3.4 Internal Clock Operation
At reset, both oscillators will be powered up; however, the relaxation oscillator will be the default clock reference for the PLL. Software should power down the block not being used and program the PLL for the correct frequency.
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CLK_MODE Relaxation OSC
XTAL Crystal OSC EXTAL
MUX
MUX
PRECS ZSRC
SYS_CLK_x2 source to the SIM
PLLCID FREF
PLLDB
PLLCOD
Prescaler (/ 1, 2, 4, 8)
FOUT PLL (X 1 - 128)
/2
FOUT/2
Postscaler (/ 1, 2, 4, 8)
Postscaler CLK
MSTR_OSC
FEEDBACK
Bus Interface & Control
MUX LCK
Bus Interface
Lock Detector
Loss of Reference Clock Detector
loss of reference clock interrupt
Figure 3-4 Internal Clock Operation
3.5 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions with the internal Relaxation Oscillator, since the 56F8322 contains this oscillator.
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Introduction
Part 4 Memory Map
4.1 Introduction
The 56F8322 device is a 16-bit motor-control chip based on the 56800E core. It uses a Harvard-style architecture with two independent memory spaces for data and program. On-chip RAM and Flash memories are used in both spaces. This section provides memory maps for: * Program Address Space, including the Interrupt Vector Table * Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for the device are summarized in Table 4-1. Flash memories' restrictions are identified in the "Use Restrictions" column of Table 4-1.
Table 4-1 Chip Memory Configurations
On-Chip Memory Program Flash Data Flash Program RAM Data RAM Program Boot Flash 56F8322 32KB 8KB 4KB 8KB 8KB Use Restrictions Erase/Program via Flash interface unit and word writes to CDBW Erase/Program via Flash interface unit and word writes to CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously. None None Erase/Program via Flash Interface unit and word writes to CDBW
4.2 Program Map
The Program Memory map is located in Table 4-2. The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) usually control the Program Memory map. Because the 56F8322 does not include EMI, the OMR MA bit, which is used to decide internal or external BOOT, will have no effect on the Program Memory Map. OMR MB reflects the security status of the Program Flash. After reset, changing the OMR MB bit will have no effect on the Program Flash.
Table 4-2 Program Memory Map at Reset
Begin/End Address P: $1F FFFF P: $03 0000 P: $02 FFFF P: $02 F800 P: $02 F7FF P: $02 1000 P: $02 0FFF P: $02 0000 RESERVED On-Chip Program RAM 4KB RESERVED Boot Flash 8KB Cop Reset Address = $02 0002 Boot Location = $02 0000 RESERVED Internal Program Flash 32KB Memory Allocation
P: $01 FFFF P: $00 4000 P: $00 3FFF P: $00 0000
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4.3 Interrupt Vector Table
Table 4-3 provides the 56F8322's reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.6.11 for the reset value of the VBA. In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions.
Table 4-3 Interrupt Vector Table Contents1
Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function Reserved for Reset Overlay2 Reserved for COP Reset Overlay2 core core core core core core core core core core core core core LVI PLL FM_ERR FM_CC FM_CBE FLEXCAN FLEXCAN FLEXCAN FLEXCAN 2 3 4 5 6 7 9 10 11 14 15 16 17 20 21 22 23 24 26 27 28 29 3 3 3 3 1-3 1-3 1-3 1-3 1-3 2 1 0 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 P:$04 P:$06 P:$08 P:$0A P:$0C P:$0E P:$12 P:$14 P:$16 P:$1C P:$1E P:$20 P:$22 P:$28 P:$2A P:$2C P:$2E P:$30 P:$34 P:$36 P:$38 P:$3A Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access OnCE Step Counter OnCE Breakpoint Unit 0 Reserved OnCE Trace Buffer OnCE Transmit Register Empty OnCE Receive Register Full Reserved SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 IRQA Reserved Low Voltage Detector (power sense) PLL FM Error Interrupt FM Command Complete FM Command, data and address Buffers Empty Reserved FLEXCAN Bus Off FLEXCAN Error FLEXCAN Wake Up FLEXCAN Message Buffer Interrupt
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Interrupt Vector Table
Table 4-3 Interrupt Vector Table Contents1 (Continued)
Peripheral Vector Number Priority Level Vector Base Address + Reserved GPIOC GPIOB GPIOA SPI1 SPI1 SPI0 SPI0 SCI1 SCI1 SCI1 SCI1 DEC0 DEC0 TMRC TMRC TMRC TMRC TMRA TMRA TMRA TMRA SCI0 SCI0 SCI0 SCI0 ADCA ADCA PWMA PWMA core 33 34 35 38 39 40 41 42 43 45 46 49 50 56 57 58 59 64 65 66 67 68 69 71 72 74 76 78 80 81 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 -1 P:$42 P:$44 P:$46 P:$4C P:$4E P:$50 P:$52 P:$54 P:$56 P:$5A P:$5C P:$62 P:$64 P:$70 P:$72 P:$74 P:$76 P:$80 P:$82 P:$84 P:$86 P:$88 P:$8A P:$8E P:$90 P:$94 P:$98 P:$9C P:$A0 P:$A2 GPIO C GPIO B GPIO A Reserved SPI 1 Receiver Full SPI 1 Transmitter Empty SPI 0 Receiver Full SPI 0 Transmitter Empty SCI 1 Transmitter Empty SCI 1Transmitter Idle Reserved SCI 1 Receiver Error SCI 1 Receiver Full Reserved Quadrature Decoder #0 Home Switch or Watchdog Quadrature Decoder #0 INDEX Pulse Reserved Timer C Channel 0 Timer C Channel 1 Timer C Channel 2 Timer C Channel 3 Reserved Timer A Channel 0 Timer A Channel 1 Timer A Channel 2 Timer A Channel 3 SCI 0 Transmitter Empty SCI 0 Transmitter Idle Reserved SCI 0 Receiver Error SCI 0 Receiver Full Reserved ADC A Conversion Complete Reserved ADC A Zero Crossing of Limit Error Reserved Reload PWM A Reserved PWM A Fault SW Interrupt LP Interrupt Function
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1. Two words are allocated for each entry in the Vector table. This does not allow the full address range to be referenced from the Vector table, providing only 19 bits of address. 2. If the VBA is set to $0200, the first two locations of the vector table will overlay the chip reset addresses.
4.4 Data Map
Table 4-4 Data Memory Map1
Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 2000 X:$00 1FFF X:$00 1000 X:$00 0FFF X:$00 0000 Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 location allocated RESERVED On-Chip Data Flash 8KB On-Chip Data RAM 8KB2
1. All addresses are 16-bit Word addresses. 2. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle, long-word operations
4.5 Flash Memory Map
Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides on the Data Memory buses and is controlled separately, having its own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control the operation of the Flash Controller. Because these words are part of the Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. In the 56F8322, these configure parameters are located between $00_3FF7 and $00_3FFF.
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Flash Memory Map
Program Memory
(BOOT_FLASH_START + $0FFF) (BOOT_FLASH_START = $02_0000)
Data Memory
FM_BASE + $14
8K Bytes Boot
Banked Registers Unbanked Registers
FM_BASE + $00
Reserved
DATA_FLASH_START + $0FFF DATA_FLASH_START + $0000
8K Bytes 8K Bytes
(PROG_FLASH_START + $00_3FFF) (PROG_FLASH_START + $00_3FF7) (PROG_FLASH_START + $00_3FF6)
Configure Field
(FM_PROG_MEM_TOP = $00_3FFF)
Block 0 Odd Block 0 Even ...
BLOCK 0 Odd (2 Bytes) $00_0003 BLOCK 0 Even (2 Bytes) $00_0002 BLOCK 0 Odd (2 Bytes) $00_0001 BLOCK 0 Even (2 Bytes) $00_0000
32K Bytes
(PROG_FLASH_START = $00_0000)
Figure 4-1 Flash Array Memory Maps
Table 4-5 shows the page and sector sizes used within each Flash memory block on the chip.
Table 4-5 Flash Memory Partitions
Flash Size Program Flash Data Flash Boot Flash 32KB 8KB 8KB Sectors 16 16 4 Sector Size 1K x 16 bits 256 x 16 bits 1K x 16 bits Page Size 512 x 16 bits 256 x 16 bits 256 x 16 bits
Please see the 56F8300 Peripheral User Manual for additional Flash information
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4.6 EOnCE Memory Map
Table 4-6 EOnCE Memory Map
Address Register Acronym Reserved X:$FF FF8A OESCR External Signal Control Register Reserved X:$FFFF8E OBCNTR Breakpoint Unit [0] Counter Reserved X:$FFFF90 X:$FFFF91 X:$FFFF92 X:$FFFF93 X:$FFFF94 X:$FFFF95 X:$FFFF96 X:$FFFF97 X:$FFFF98 X:$FFFF99 X:$FFFF9A X:$FFFF9B X:$FFFF9C X:$FFFF9D X:$FFFF9E X:$FFFF9F :X:$FFFFA0 OBMSK (32 bits) -- OBAR2 (32 bits) -- OBAR1 (24 bits) -- OBCR (24 bits) -- OTB (21-24 bits/stage) -- OTBPR (8 bits) OTBCR OBASE (8 bits) OSR OSCNTR (24 bits) -- OCR (bits) Breakpoint 1 Unit [0] Mask Register Breakpoint 1 Unit [0] Mask Register Breakpoint 2 Unit [0] Address Register Breakpoint 2 Unit [0] Address Register Breakpoint 1 Unit [0] Address Register Breakpoint 1 Unit [0] Address Register Breakpoint Unit [0] Control Register Breakpoint Unit [0] Control Register Trace Buffer Register Stages Trace Buffer Register Stages Trace Buffer Pointer Register Trace Buffer Control Register Peripheral Base Address Register Status Register Instruction Step Counter Instruction Step Counter Control Register Reserved X:$FFFFFC X:$FFFFFD X:$FFFFFE X:$FFFFFF OCLSR (8 bits) OTXRXSR (8 bits) OTX/ORX (32 bits) OTX1/ORX1 Core Lock/Unlock Status Register Transmit and Receive Status and Control Register Transmit Register / Receive Register Transmit Register Upper Word Receive Register Upper Word Register Name
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read/written using word accesses only. Table 4-7 summarizes base addresses for the set of peripherals on the 56F8322 device. Peripherals are listed in order of the base address.
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Peripheral Memory Mapped Registers
The following tables list all of the peripheral registers required to control or access the peripherals.
Table 4-7 Data Memory Peripheral Base Address Map Summary
Peripheral Timer A Timer C PWM A Quadrature Decoder 0 ITCN ADC A Temperature Sensor SCI #0 SCI #1 SPI #0 SPI #1 COP PLL, OSC GPIO Port A GPIO Port B GPIO Port C SIM Power Supervisor FM FlexCAN TMRA TMRC PWMA DEC0 ITCN ADCA TSENSOR SCI0 SCI1 SPI0 SPI1 COP CLKGEN GPIOA GPIOB GPIOC SIM LVI FM FC Prefix Base Address X:$00 F040 X:$00 F0C0 X:$00 F140 X:$00 F180 X:$00 F1A0 X:$00 F200 X:$00 F270 X:$00 F280 X:$00 F290 X:$00 F2A0 X:$00 F2B0 X:$00 F2C0 X:$00 F2D0 X:$00 F2E0 X:$00 F300 X:$00 F310 X:$00 F350 X:$00 F360 X:$00 F400 X:$00 F800 Table Number 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27
Table 4-8 Quad Timer A Registers Address Map (TMRA_BASE = $00F040)
Register Acronym TMRA0_CMP1 TMRA0_CMP2 TMRA0_CAP TMRA0_LOAD TMRA0_HOLD TMRA0_CNTR TMRA0_CTRL TMRA0_SCR TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRA1_CMP1 $10 Compare Register 1
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Table 4-8 Quad Timer A Registers Address Map (TMRA_BASE = $00F040) (Continued)
Register Acronym TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR Address Offset $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A Register Description Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSCR $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register
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Peripheral Memory Mapped Registers
Table 4-9 Quad Timer C Registers Address Map (TMRC_BASE = $00F0C0)
Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRC3_CMP1 $30 Compare Register 1
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Table 4-9 Quad Timer C Registers Address Map (TMRC_BASE = $00F0C0) (Continued)
Register Acronym TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Address Offset $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Register Description Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register
Table 4-10 Pulse Width Modulator A Registers Address Map (PWMA_BASE = $00F140)
Register Acronym PWMA_PMCTRL PWMA_PMFCTRL PWMA_PMFSA PWMA_PMOUT PWMA_PMCNT PWMA_PWMCM PWMA_PWMVAL0 PWMA_PWMVAL1 PWMA_PWMVAL2 PWMA_PWMVAL3 PWMA_PWMVAL4 PWMA_PWMVAL5 PWMA_PMDEADTM PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 Control Register Fault Control Register Fault Status Acknowledge Register Output Control Register Counter Register Counter Modulo Register Value Register 0 Value Register 1 Value Register 2 Value Register 3 Value Register 4 Value Register 5 Dead Time Register Disable Mapping Register 1 Disable Mapping Register 2 Configure Register Channel Control Register Port Register Internal Correction Control Register Description
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Table 4-11 Quadrature Decoder 0 Registers Address Map (DEC0_BASE = $00F180)
Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV DEC0_REVH DEC0_UPOS DEC0_LPOS DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D Register Description Decoder Control Register Filter Interval Register Watchdog Timeout Register Position Difference Counter Register Position Difference Counter Hold Register Revolution Counter Register Revolution Hold Register Upper Position Counter Register Lower Position Counter Register Upper Position Hold Register Lower Position Hold Register Upper Initialization Register Lower Initialization Register Input Monitor Register
Table 4-12 Interrupt Control Registers Address Map (ITCN_BASE = $00F1A0)
Register Acronym IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 IRQP 2 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 Register Description Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 Interrupt Priority Register 8 Interrupt Priority Register 9 Vector Base Address Register Fast Interrupt Match Register 0 Fast Interrupt Vector Address Low 0 Register Fast Interrupt Vector Address High 0 Register Fast Interrupt Match Register 1 Fast Interrupt Vector Address Low 0 Register Fast Interrupt Vector Address High 0 Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2
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Table 4-12 Interrupt Control Registers Address Map (ITCN_BASE = $00F1A0) (Continued)
Register Acronym IRQP 3 IRQP 4 IRQP 5 Address Offset $14 $15 $16 Register Description IRQ Pending Register 3 IRQ Pending Register 4 IRQ Pending Register 5 Reserved ICTL $1D Interrupt Control Register
Table 4-13 Analog to Digital Converter Registers Address Map (ADCA_BASE = $00F200)
Register Acronym ADCA_CR1 ADCA_CR2 ADCA_ZCC ADCA_LST 1 ADCA_LST 2 ADCA_SDIS ADCA_STAT ADCA_LSTAT ADCA_ZCSTAT ADCA_RSLT 0 ADCA_RSLT 1 ADCA_RSLT 2 ADCA_RSLT 3 ADCA_RSLT 4 ADCA_RSLT 5 ADCA_RSLT 6 ADCA_RSLT 7 ADCA_LLMT 0 ADCA_LLMT 1 ADCA_LLMT 2 ADCA_LLMT 3 ADCA_LLMT 4 ADCA_LLMT 5 ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C Register Description Control Register 1 Control Register 2 Zero Crossing Control Register Channel List Register 1 Channel List Register 2 Sample Disable Register Status Register Limit Status Register Zero Crossing Status Register Result Register 0 Result Register 1 Result Register 2 Result Register 3 Result Register 4 Result Register 5 Result Register 6 Result Register 7 Low Limit Register 0 Low Limit Register 1 Low Limit Register 2 Low Limit Register 3 Low Limit Register 4 Low Limit Register 5 Low Limit Register 6 Low Limit Register 7 High Limit Register 0 High Limit Register 1 High Limit Register 2 High Limit Register 3
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Table 4-13 Analog to Digital Converter Registers Address Map (ADCA_BASE = $00F200) (Continued)
Register Acronym ADCA_HLMT 4 ADCA_HLMT 5 ADCA_HLMT 6 ADCA_HLMT 7 ADCA_OFS 0 ADCA_OFS 1 ADCA_OFS 2 ADCA_OFS 3 ADCA_OFS 4 ADCA_OFS 5 ADCA_OFS 6 ADCA_OFS 7 ADCA_POWER ADCA_CAL Address Offset $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Register Description High Limit Register 4 High Limit Register 5 High Limit Register 6 High Limit Register 7 Offset Register 0 Offset Register 1 Offset Register 2 Offset Register 3 Offset Register 4 Offset Register 5 Offset Register 6 Offset Register 7 Power Control Register Calibration Register
Table 4-14 Temperature Sensor Register Address Map (TSENSOR_BASE = $00F270)
Register Acronym TSENSOR_CNTL Address Offset $0 Control Register Register Description
Table 4-15 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00F280)
Register Acronym SCI0_SCIBR SCI0_SCICR Address Offset $0 $1 Register Description Baud Rate Register Control Register Reserved SCI0_SCISR SCI0_SCIDR $3 $4 Status Register Data Register
Table 4-16 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00F290)
Register Acronym SCI1_SCIBR SCI1_SCICR Address Offset $0 $1 Register Description Baud Rate Register Control Register Reserved SCI1_SCISR SCI1_SCIDR $3 $4 Status Register Data Register
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Table 4-17 Serial Peripheral Interface 0 Registers Address Map (SPI0_BASE = $00F2A0)
Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Address Offset $0 $1 $2 $3 Register Description Status and Control Register Data Size Register Data Receive Register Data Transmitter Register
Table 4-18 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00F2B0)
Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR SPI1_SPDTR Address Offset $0 $1 $2 $3 Register Description Status and Control Register Data Size Register Data Receive Register Data Transmitter Register
Table 4-19 Computer Operating Properly Registers Address Map (COP_BASE = $00F2C0)
Register Acronym COPCTL COPTO COPCTR Address Offset $0 $1 $2 Control Register Time Out Register Counter Register Register Description
Table 4-20 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00F2D0)
Register Acronym PLLCR PLLDB PLLSR Address Offset $0 $1 $2 Control Register Divide-By Register Status Register Reserved SHUTDOWN OSCTL $4 $5 Shutdown Register Oscillator Control Register Register Description
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Table 4-21 GPIOA Registers Address Map (GPIOA_BASE = $00F2E0)
Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER GPIOA_IAR GPIOA_IENR GPIOA_IPOLR GPIOA_IPR GPIOA_IESR GPIOA_PPMODE GPIOA_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 0FFF 0 x 0000 0 x 0000 0 x 0FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0FFF -
Table 4-22 GPIOB Registers Address Map (GPIOB_BASE = $00F300)
Register Acronym GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 00FF 0 x 0000 0 x 0000 0 x 00FF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 00FF -
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Table 4-23 GPIOC Registers Address Map (GPIOC_BASE = $00F310)
Register Acronym GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 007C 0 x 0000 0 x 0000 0 x 007F 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 007F -
Table 4-24 System Integration Module Registers Address Map (SIM_BASE = $00F350)
Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half JTAG ID Least Significant Half JTAG ID Pull-up Disable Register Reserved SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL $A $B $C $D $E Clock Out Select Register GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register Register Description
Table 4-25 Power Supervisor Registers Address Map (LVI_BASE = $00F360)
Register Acronym LVI_CONTROL LVI_STATUS Address Offset $0 $1 Control Register Status Register Register Description
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Table 4-26 Flash Module Registers Address Map (FM_BASE = $00F400)
Register Acronym FMCLKD FMMCR FMSECH FMSECL FMMNTR FMPROT FMPROTB FMUSTAT FMCMD FMCTL FMIFROPT 0 Address Offset $0 $1 $3 $4 $5 $10 $11 $13 $14 $15 $1A Register Description Clock Divider Register Module Control Register Reserved Security High Half Register Security Low Half Register Monitor Data Register Reserved Protection Register (Banked) Protection Boot Register (Banked) Reserved User Status Register (Banked) Command Register (Banked) Control Register (Banked) Reserved 16-Bit Information Option Register 0 Hot temperature ADC reading of Temp Sense; value set during factory test 16-Bit Information Option Register 1 Trim cap setting of the relaxation oscillator 16-Bit Information Option Register 2 Room temperature ADC reading of Temp Sense; value set during factory test
FMIFROPT 1 FMIFROPT 2
$1B $1C
Table 4-27 FlexCAN Registers Address Map (TMRD_BASE = $00F800)
Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR FCMAXMB FCIMASK2 FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L Address Offset $0 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D Register Description Module Configuration Register Reserved Control Register 0 Register Control Register 1 Register Free Running Timer Register Maximum Message Buffer Configuration Register Interrupt Masks 2 Register Receive Global Mask High Register Receive Global Mask Low Register Receive Buffer 14 Mask High Register Receive Buffer 14 Mask Low Register Receive Buffer 15 Mask High Register Receive Buffer 15 Mask Low Register
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Table 4-27 FlexCAN Registers Address Map (TMRD_BASE = $00F800) (Continued)
Register Acronym Address Offset Reserved FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCIFLAG 2 FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA $10 $11 $12 $13 $1B $40 $41 $42 $43 $44 $45 $46 $48 $49 $4A $4B $4C $4D $4E $50 $51 $52 $53 $54 $55 $56 $58 $59 $5A $5B $5C $5D $5E Error and Status Register Interrupt Masks 1 Register Interrupt Flags 1 Register Receive and Transmit Error Counters Register Reserved Interrupt Flags 2 Register Reserved Message Buffer 0 Control/Status Register Message Buffer 0 ID High Register Message Buffer 0 ID Low Register Message Buffer 0 Data Register Message Buffer 0 Data Register Message Buffer 0 Data Register Message Buffer 0 Data Register Reserved Message Buffer 1 Control/Status Register Message Buffer 1 ID High Register Message Buffer 1 ID Low Register Message Buffer 1 Data Register Message Buffer 1 Data Register Message Buffer 1 Data Register Message Buffer 1 Data Register Reserved Message Buffer 2 Control/Status Register Message Buffer 2 ID High Register Message Buffer 2 ID Low Register Message Buffer 2 Data Register Message Buffer 2 Data Register Message Buffer 2 Data Register Message Buffer 2 Data Register Reserved Message Buffer 3 Control/Status Register Message Buffer 3 ID High Register Message Buffer 3 ID Low Register Message Buffer 3 Data Register Message Buffer 3 Data Register Message Buffer 3 Data Register Message Buffer 3 Data Register Reserved Register Description
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Table 4-27 FlexCAN Registers Address Map (TMRD_BASE = $00F800) (Continued)
Register Acronym FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB5_CONTROL FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA Address Offset $60 $61 $62 $63 $64 $65 $66 $68 $69 $6A $6B $6C $6D $6E $70 $71 $72 $73 $74 $75 $76 $78 $79 $7A $7B $7C $7D $7E $80 $81 $82 $83 $84 $85 $86 Register Description Message Buffer 4 Control/Status Register Message Buffer 4 ID High Register Message Buffer 4 ID Low Register Message Buffer 4 Data Register Message Buffer 4 Data Register Message Buffer 4 Data Register Message Buffer 4 Data Register Reserved Message Buffer 5 Control/Status Register Message Buffer 5 ID High Register Message Buffer 5 ID Low Register Message Buffer 5 Data Register Message Buffer 5 Data Register Message Buffer 5 Data Register Message Buffer 5 Data Register Reserved Message Buffer 6 Control/Status Register Message Buffer 6 ID High Register Message Buffer 6 ID Low Register Message Buffer 6 Data Register Message Buffer 6 Data Register Message Buffer 6 Data Register Message Buffer 6 Data Register Reserved Message Buffer 7 Control/Status Register Message Buffer 7 ID High Register Message Buffer 7 ID Low Register Message Buffer 7 Data Register Message Buffer 7 Data Register Message Buffer 7 Data Register Message Buffer 7 Data Register Reserved Message Buffer 8 Control/Status Register Message Buffer 8 ID High Register Message Buffer 8 ID Low Register Message Buffer 8 Data Register Message Buffer 8 Data Register Message Buffer 8 Data Register Message Buffer 8 Data Register Reserved
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Table 4-27 FlexCAN Registers Address Map (TMRD_BASE = $00F800) (Continued)
Register Acronym FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA Address Offset $88 $89 $8A $8B $8C $8D $8E $90 $91 $92 $93 $94 $95 $96 $98 $99 $9A $9B $9C $9D $9E $A0 $A1 $A2 $A3 $A4 $A5 $A6 $A8 $A9 $AA $AB $AC $AD $AE Register Description Message Buffer 9 Control/Status Register Message Buffer 9 ID High Register Message Buffer 9 ID Low Register Message Buffer 9 Data Register Message Buffer 9 Data Register Message Buffer 9 Data Register Message Buffer 9 Data Register Reserved Message Buffer 10 Control/Status Register Message Buffer 10 ID High Register Message Buffer 10 ID Low Register Message Buffer 10 Data Register Message Buffer 10 Data Register Message Buffer 10 Data Register Message Buffer 10 Data Register Reserved Message Buffer 11 Control/Status Register Message Buffer 11 ID High Register Message Buffer 11 ID Low Register Message Buffer 11 Data Register Message Buffer 11 Data Register Message Buffer 11 Data Register Message Buffer 11 Data Register Reserved Message Buffer 12 Control/Status Register Message Buffer 12 ID High Register Message Buffer 12 ID Low Register Message Buffer 12 Data Register Message Buffer 12 Data Register Message Buffer 12 Data Register Message Buffer 12 Data Register Reserved Message Buffer 13 Control/Status Register Message Buffer 13 ID High Register Message Buffer 13 ID Low Register Message Buffer 13 Data Register Message Buffer 13 Data Register Message Buffer 13 Data Register Message Buffer 13 Data Register Reserved
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Table 4-27 FlexCAN Registers Address Map (TMRD_BASE = $00F800) (Continued)
Register Acronym FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA Address Offset $B0 $B1 $B2 $B3 $B4 $B5 $B6 $B8 $B9 $BA $BB $BC $BD $BE Register Description Message Buffer 14 Control/Status Register Message Buffer 14 ID High Register Message Buffer 14 ID Low Register Message Buffer 14 Data Register Message Buffer 14 Data Register Message Buffer 14 Data Register Message Buffer 14 Data Register Reserved Message Buffer 15 Control/Status Register Message Buffer 15 ID High Register Message Buffer 15 ID Low Register Message Buffer 15 Data Register Message Buffer 15 Data Register Message Buffer 15 Data Register Message Buffer 15 Data Register Reserved
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Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs) and to signal to the 56800E core when an interrupt of sufficient priority exists and to what address to jump in order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features: * Programmable priority levels for each IRQ * Two programmable Fast Interrupts * Notification to SIM module to restart clocks out of Wait and Stop modes * Drives initial address on the address bus after reset For further information, see Table 4-3, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number 81 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the vector number to determine the vector address. In this way, an offset is generated into the vector table for each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level.
Table 5-1 Interrupt Mask Bit Definition
SR[9]1 0 0 1 1 SR[8]1 0 1 0 1 Permitted Exceptions Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3 Masked Exceptions None Priority 0 Priorities 0, 1 Priorities 0, 1, 2
1. Core status register bits indicating current interrupt mask within the core.
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Table 5-2. Interrupt Priority Encoding
IPIC_LEVEL[1:0]1 00 01 10 11 Current Interrupt Priority Level No Interrupt or SWILP Priority 0 Priority 1 Priorities 2 or 3 Required Nested Exception Priority Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3
1. See IPIC field definition in Section 5.6.30.2
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A fast interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number 3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts its fast interrupt handling.
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5.4 Block Diagram
Priority Level any0 Level 0 82 -> 7 Priority Encoder
7
INT1
2 -> 4 Decode
INT VAB CONTROL IPIC
any3 Level 3 Priority Level 82 -> 7 Priority Encoder
IACK SR[9:8] PIC_EN
7
INT82
2 -> 4 Decode
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation: * * Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA signal automatically becomes low-level sensitive in these modes, even if the control register bits are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling edge. A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during STOP mode. The FlexCAN module can wake the device from STOP, and a reset will do just that, or IRQA and IRQB can wake it up.
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5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.
Table 5-3 ITCN Register Summary (ITCN_BASE = $00F1A0)
Register Acronym IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 IRQP3 IRQP4 IRQP5 Base Address + $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 Interrupt Priority Register 8 Interrupt Priority Register 9 Vector Base Address Register Fast Interrupt 0 Match Register Fast Interrupt 0 Vector Address Low Register Fast Interrupt 0 Vector Address High Register Fast Interrupt 1 Match Register Fast Interrupt 1 Vector Address Low Register Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 IRQ Pending Register 3 IRQ Pending Register 4 IRQ Pending Register 5 Reserved ICTL $1D Interrupt Control Register 5.6.30 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 5.6.20 5.6.21 5.6.22 5.6.23
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Add. Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15
Register Name IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 IRQP3 IRQP4 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
15
0 0
14
0 0
13
12
11
10
9
0 0
8
0 0
7
0 0
6
0 0
5
0
4
0
3
0
2
0
1
0
0
0
BKPT_ U0 IPL 0 0
STPCNT IPL 0 0
RX_REG IPL 0 0
TX_REG IPL 0 0
TRBUF IPL IRQA IPL 0 0
FMCBE IPL 0 0
FMCC IPL 0 0
FMERR IPL 0 0
LOCK IPL FCMSGBUF IPL 0 0
LVI IPL FCWKUP IPL 0 0 0 0 0 0 0 0
FCERR IPL GPIOA IPL SCI1_TIDL IPL 0 0 0 0
FCBOFF IPL GPIOB IPL SCI1_XMIT IPL DEC0_XIRQ IPL TMRC2 IPL TMRA2 IPL ADCA_CC IPL
SPI0_RCV IPL 0 0
SPI1_XMIT IPL 0 0 0 0 0 0
SPI1_RCV IPL SCI1_RCV IPL 0 0 0 0 0 0
GPIOC IPL SPI0_XMIT IPL DEC0_HIRQ IPL TMRC1 IPL TMRA1 IPL 0 0
SCI1_RERR IPL 0 0 0 0
TMRC0 IPL TMRA0 IPL SCI0_RCV IPL PWMA F IPL 0 0 0 0
TMRC3 IPL TMRA3 IPL 0 0
SCI0_RERR IPL 0 0 0 0 0
SCI0_TIDL IPL 0 0
SCI0_XMIT IPL ADCA_ZC IPL
PWMA_RL IPL
VECTOR BASE ADDRESS 0 0 0 0 0 FAST INTERRUPT 0
FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT 1
FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH 1
PENDING [16:2] PENDING [32:17] PENDING [48:33] PENDING [64:49] PENDING [80:65]
$16
IRQP5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PENDING [81]
$1D
ICTL
R W R W
INT
IPIC
VAB
INT_ DIS
1
0
IRQA STATE
0
IRQA EDG
0
= Read as 0 = Reserved
Figure 5-2 ITCN Register Map Summary
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5.6.1
Base + $0 Read Write RESET
Interrupt Priority Register 0 (IPR0)
15
0
14
0
13
12
11
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
BKPT_U0IPL 0 0
STPCNT IPL 0 0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1 5.6.1.2
Reserved--Bits 15-14 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)-- Bits13-12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)-- Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.4
Reserved--Bits 9-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2
Base + $1 Read Write RESET
Interrupt Priority Register 1 (IPR1)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
RX_REG IPL 0 0
TX_REG IPL 0 0
TRBUF IPL 0 0
0
0
0
0
0
0
0
0
0
0
Figure 5-4 Interrupt Priority Register 1 (IPR1)
5.6.2.1
Reserved--Bits 15-6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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5.6.2.2
EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)--Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2
5.6.2.3
EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.2.4
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)-- Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.3
Base + $2 Read Write RESET
Interrupt Priority Register 2 (IPR2)
15 14 13 12 11 10 9 8 7 6 5
0
4
0
3
0
2
0
1
0
FMCBE IPL 0 0
FMCC IPL 0 0
FMERR IPL 0 0
LOCK IPL 0 0
LVI IPL 0 0
IRQA IPL 0 0
0
0
0
0
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1
Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)--Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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Register Descriptions
5.6.3.2
Flash Memory Command Complete Priority Level (FMCC IPL)--Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.3
Flash Memory Error Interrupt Priority Level (FMERR IPL)--Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.4
PLL Loss of Lock Interrupt Priority Level (LOCK IPL)--Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.5
Low Voltage Detector Interrupt Priority Level (LVI IPL)--Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.6
Reserved--Bits 5-2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
MOTOROLA
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51
5.6.3.7
External IRQ A Interrupt Priority Level (IRQA IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4
Base + $3 Read Write RESET
Interrupt Priority Register 3 (IPR3)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
0
0
FCMSGBUF IPL 0 0
FCWKUP IPL 0 0
FCERR IPL 0 0
FCBOFF IPL 0 0
0
0
0
0
0
0
0
0
Figure 5-6 Interrupt Priority Register 3 (IPR3)
5.6.4.1 5.6.4.2
Reserved--Bits 15-10 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)--Bits 9-8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.3
FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)-- Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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Register Descriptions
5.6.4.4
FlexCAN Error Interrupt Priority Level (FCERR IPL)-- Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.5
FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)-- Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.6
Reserved--Bits 1-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5
Base + $4 Read Write RESET
Interrupt Priority Register 4 (IPR4)
15 14 13 12 11 10 9
0
8
0
7
0
6
0
5
4
3
2
1
0
SPI0_RCV IPL 0 0
SPI1_XMIT IPL 0 0
SPI1_RCV IPL 0 0
GPIOA IPL 0 0
GPIOB IPL 0 0
GPIOC IPL 0 0
0
0
0
0
Figure 5-7 Interrupt Priority Register 4 (IPR4)
5.6.5.1
SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)-- Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
MOTOROLA
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5.6.5.2
SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)-- Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.3
SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)-- Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.4 5.6.5.5
Reserved--Bits 9-6 GPIO_A Interrupt Priority Level (GPIOA IPL)--Bits 5-4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.6
GPIO_B Interrupt Priority Level (GPIOB IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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Register Descriptions
5.6.5.7
GPIO_C Interrupt Priority Level (GPIOC IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6
Base + $5 Read Write RESET
Interrupt Priority Register 5 (IPR5)
15
0
14
0
13
0
12
0
11
10
9
8
7
0
6
0
5
4
3
2
1
0
SCI1_RCV IPL 0 0
SCI1_RERR IPL 0 0
SCI1_TIDL IPL 0 0
SCI1_XMIT IPL 0 0
SPI0_XMIT IPL 0 0
0
0
0
0
0
0
Figure 5-8 Interrupt Priority Register 5 (IPR5)
5.6.6.1 5.6.6.2
Reserved--Bits 15-12 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)-- Bits 11-10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.3
SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)-- Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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5.6.6.4 5.6.6.5
Reserved--Bits 7-6 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)-- Bits 5-4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.6
SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)-- Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.7
SPI0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)-- Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7
Base + $6 Read Write RESET
Interrupt Priority Register 6 (IPR6)
15 14 13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
TMRC0 IPL 0 0
DEC0_XIRQ IPL 0 0
DEC0_HIRQ IPL 0 0
0
0
0
0
0
0
0
0
0
0
Figure 5-9 Interrupt Priority Register 6 (IPR6)
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56F8322 Technical Data Preliminary
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Register Descriptions
5.6.7.1
Timer C Channel 0 Interrupt Priority Level (TMRC_0 IPL)-- Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.2 5.6.7.3
Reserved--Bits 13-4 Quadrature Decoder 0 INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)--Bits 3-2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.4
Quadrature Decoder 0 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8
Base + $7 Read Write RESET
Interrupt Priority Register 7 (IPR7)
15 14 13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
TMRA0 IPL 0 0
TMRC3 IPL 0 0
TMRC2 IPL 0 0
TMRC1 IPL 0 0
0
0
0
0
0
0
0
0
Figure 5-10 Interrupt Priority Register (IPR7)
MOTOROLA
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5.6.8.1
Timer A Channel 0 Interrupt Priority Level (TMRA0 IPL)-- Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8.2 5.6.8.3
Reserved--Bits 13-6 Timer C Channel 3 Interrupt Priority Level (TMRC3 IPL)--Bits 5-4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8.4
Timer C Channel 2 Interrupt Priority Level (TMRC2 IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8.5
Timer C Channel 1 Interrupt Priority Level (TMRC1 IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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Register Descriptions
5.6.9
Base + $8 Read Write RESET
Interrupt Priority Register 8 (IPR8)
15 14 13 12 11
0
10
0
9
8
7
6
5
4
3
2
1
0
SCI0_RCV IPL 0 0
SCI0_RERR IPL 0 0
SCI0_TIDL IPL 0 0
SCI0_XMIT IPL 0 0
TMRA3 IPL 0 0
TMRA2 IPL 0 0
TMRA1 IPL 0 0
0
0
Figure 5-11 Interrupt Priority Register 8 (IPR8)
5.6.9.1
SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)-- Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.2
SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)-- Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.3 5.6.9.4
Reserved--Bits 11-10 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)-- Bits 9-8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
MOTOROLA
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5.6.9.5
SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)-- Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.6
Timer A Channel 3 Interrupt Priority Level (TMRA3 IPL)--Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.7
Timer A Channel 2 Interrupt Priority Level (TMRA2 IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.8
Timer A Channel 1 Interrupt Priority Level (TMRA1 IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10
Base + $9 Read Write RESET
Interrupt Priority Register 9 (IPR9)
15 14 13
0
12
0
11
10
9
0
8
0
7
6
5
0
4
0
3
2
1
0
0
0
PWMAF IPL 0 0
PWMA_RL IPL 0 0
ADCA_ZC IPL 0 0
ADCA_CC IPL 0 0
0
0
0
0
0
0
0
0
Figure 5-12 Interrupt Priority Register 9 (IPR9)
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56F8322 Technical Data Preliminary
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Register Descriptions
5.6.10.1
PWM A Fault Interrupt Priority Level (PWMAF IPL)--Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.2 5.6.10.3
Reserved--Bits 13-12 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)-- Bits 11-10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.4 5.6.10.5
Reserved--Bits 9-8 ADC A Zero Crossing Interrupt Priority Level (ADCA_ZC IPL)-- Bits 7-6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.6 5.6.10.7
Reserved--Bits 5-4 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)--Bits 3-2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
56F8322 Technical Data Preliminary 61
MOTOROLA
5.6.10.8
Reserved--Bits 1-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.11
Base + $A Read Write RESET
Vector Base Address Register (VBA)
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
3
2
1
0
VECTOR BASE ADDRESS 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
Figure 5-13 Vector Base Address Register (VBA)
5.6.11.1 5.6.11.2
Reserved--Bits 15-13 Interrupt Vector Base Address (VECTOR BASE ADDRESS)-- Bits 12-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt Vector Address. The lower eight bits of the ISR address are determined based upon the highest-priority interrupt; see Section 5.3.1 for details.
5.6.12
Base + $B Read Write RESET
Fast Interrupt 0 Match Register (FIM0)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
FAST INTERRUPT 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
5.6.12.1 5.6.12.2
Reserved--Bits 15-7 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)--Bits 6-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Section 5.3.3 for details. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest priority level 2 interrupt regardless of their location in the interrupt table prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-3.
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Register Descriptions
5.6.13
Base + $C Read Write RESET
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.13.1
Fast Interrupt 0 Vector Address Low (FIVAL0)--Bits 15-0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.14
Base + $D Read Write RESET
Fast Interrupt 0 Vector Address High Register (FIVAH0)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
FAST INTERRUPT 0 VECTOR ADDRESS HIGH 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.14.1 5.6.14.2
Reserved--Bits 15-5 Fast Interrupt 0 Vector Address High (FIVAH0)--Bits 4-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15
Base + $E Read Write RESET
Fast Interrupt 1 Match Register (FIM1)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
FAST INTERRUPT 1 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
5.6.15.1 5.6.15.2
Reserved--Bits 15-7 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)--Bits 6-0
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Section 5.3.3 for details. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-3.
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5.6.16
Base + $F Read Write RESET
Fast Interrupt 1 Vector Address Low Register (FIVAL1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.16.1
Fast Interrupt 1 Vector Address Low (FIVAL1)--Bits 15-0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.17
Base + $10 Read Write RESET
Fast Interrupt 1 Vector Address High Register (FIVAH1)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
FAST INTERRUPT 1 VECTOR ADDRESS HIGH 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.17.1 5.6.17.2
Reserved--Bits 15-5 Fast Interrupt 1 Vector Address High (FIVAH1)--Bits 4-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.18
Base + $11 Read Write RESET
IRQ Pending 0 Register (IRQP0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 PENDING [16:2]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-20 IRQ Pending 0 Register (IRQP0)
5.6.18.1
IRQ Pending (PENDING)--Bits 16-2
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.18.2
Reserved--Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
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5.6.19
Read Write RESET
IRQ Pending 1 Register (IRQP1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDING [32:17]
$Base + $12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-21 IRQ Pending 1 Register (IRQP1)
5.6.19.1
IRQ Pending (PENDING)--Bits 32-17
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.20
Base + $13 Read Write RESET
IRQ Pending 2 Register (IRQP2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDING [48:33]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-22 IRQ Pending 2 Register (IRQP2)
5.6.20.1
IRQ Pending (PENDING)--Bits 48-33
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.21
Base + $14 Read Write RESET
IRQ Pending 3 Register (IRQP3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDING [64:49]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-23 IRQ Pending 3 Register (IRQP3)
5.6.21.1
IRQ Pending (PENDING)--Bits 64-49
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
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5.6.22
Base + $15 Read Write RESET
IRQ Pending 4 Register (IRQP4)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDING [80:65]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-24 IRQ Pending 4 Register (IRQP4)
5.6.22.1
IRQ Pending (PENDING)--Bits 80-65
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.23
Base + $16 Read Write RESET
IRQ Pending 5 Register (IRQP5)
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
PENDING [81]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-25 IRQ Pending Register 5 (IRQP5)
5.6.23.1 5.6.23.2
Reserved--Bits 96-82 IRQ Pending (PENDING)--Bit 81
This bit field is reserved or not implemented. The bits are read as one and cannot be modified by writing.
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.24 5.6.25 5.6.26 5.6.27 5.6.28 5.6.29
Reserved--Base + 17 Reserved--Base + 18 Reserved--Base + 19 Reserved--Base + 1A Reserved--Base + 1B Reserved--Base + 1C
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Register Descriptions
5.6.30
Base + $1D Read Write RESET
ITCN Control Register (ICTL)
15
INT
14
IPIC
13
12 11 10
9
VAB
8
7
6
5
INT_DIS
4
1
3
0
2
IRQA STATE
1
0
0
IRQA EDG 0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1
* *
Interrupt (INT)--Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core. 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core
5.6.30.2
Interrupt Priority Level (IPIC)--Bits 14-13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: * * * * Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 00 = Required nested exception priority levels are 0, 1, 2, or 3 01 = Required nested exception priority levels are 1, 2, or 3 10 = Required nested exception priority levels are 2 or 3 11 = Required nested exception priority level is 3
5.6.30.3
Vector Number - Vector Address Bus (VAB)--Bits 12-6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it.
5.6.30.4
* *
Interrupt Disable (INT_DIS)--Bit 5
This bit allows all interrupts to be disabled. 0 = Normal operation (default) 1 = All interrupts disabled
5.6.30.5 5.6.30.6 5.6.30.7
Reserved--Bit 4-3 IRQA State Pin (IRQA STATE)--Bit 2 Reserved--Bit 1
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
This read-only bit reflects the state of the external IRQA pin.
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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5.6.30.8
IRQA Edge Pin (IRQA Edg)--Bit 0
This bit controls whether the external IRQA interrupt is edge or level sensitive. During Stop and Wait modes, it is automatically level sensitive. * * 0 = IRQA interrupt is a low-level sensitive (default) 1 = IRQA interrupt is falling-edge sensitive.
5.7 Resets
5.7.1 Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released.
5.7.2
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities: Illegal Instruction, SW Interrupt 3, HW Stack Overflow, Misaligned Long Word Access, SW Interrupt 2, SW Interrupt 1, SW Interrupt 0, and SW Interrupt LP. These interrupts are enabled at their fixed priority levels.
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Introduction
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system integration module is responsible for the following functions: * * * * * * * Reset sequencing Clock control & distribution STOP/WAIT control Pull-up enables for selected peripherals System status registers Registers for software access to the JTAG ID of the chip Enforcing Flash security
6.2 Features
The SIM has the following features: * * * Flash security feature prevents unauthorized access to code/data contained in on-chip flash memory Power-Saving Clock gating for peripherals Three power modes (Run, Wait, Stop) to control power utilization -- Stop mode shuts down the 56800E core, system clock, and peripheral clock -- Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart) -- Wait mode shuts down the 56800E core and unnecessary system clock operation -- Run mode supports full part operation * * * * * * Controls to enable/disable the 56800E core WAIT and STOP instructions Controls reset sequencing after reset Software-initiated reset Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control System Control Register Registers for software access to the JTAG ID of the chip
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: * Reset Mode, which has two submodes: -- Total Reset Mode 56800E Core and all peripherals are reset -- Core-Only Reset Mode 56800E Core in reset, peripherals are active This mode is required to provide the on-chip Flash interface module time to load data from Flash into FM registers.
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*
*
*
*
Run Mode This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation. Debug Mode 56800E is in debug mode (controlled via JTAG/EOnCE). All peripherals continue to run, except the COP and PWMs. COP is disabled and PWM outputs are optionally switched off to disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details. Wait Mode In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped. Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other peripherals continue to run. Stop Mode 56800E, memory and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode.
6.4 Operating Mode Register
Bit Type RESET 15
NL R/W 0 0 0 0 0 0 0
14
13
12
11
10
9
8
CM R/W 0
7
XP R/W 0
6
SD R/W 0
5
R R/W 0
4
SA R/W 0
3
EX R/W 0
2
0
1
MB R/W
0
MA R/W 0
0
0
Figure 6-1 OMR
See Section 4.2 for detailed information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. The EX bit is not functional in this device since there is no external memory interface. For all other bits see, Section 8.2.1 of the 56F8300 Peripheral User Manual. Note: The OMR is not a Memory Map register, it is directly accessible in code through the acronym OMR.
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Register Descriptions
6.5 Register Descriptions
Table 6-1 SIM Registers (SIM_BASE = $00F350)
Address Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR Address Offset Base + $0 Base + $1 Base + $2 Base + $3 Base + $4 Base + $5 Base + $6 Base + $7 Base + $8 Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID Least Significant Half of JTAG ID Pull-up Disable Register Reserved SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL Base + $A Base + $B Base + $C Base + $D Base + $E CLKO Select Register GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register 6.5.7 6.5.7 6.5.8 6.5.9 6.5.10 Section Location 6.5.1 6.5.2 6.5.3 6.5.3 6.5.3 6.5.3 6.5.4 6.5.5 6.5.6
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Add. Offset $0 $1 $2 $3 $4 $5 $6 $7
Register Name SIM_ CONTROL SIM_ RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ ID SIM_LSH_ID R W R W R W R W R W R W R W R W R
15
0 0
14
0 0
13
O O
12
0 0
11
0 0
10
0 0
9
0 0
8
0 0
7
0 0
6
0 0
5
Once Ebl0 SWR
4
SW Rst
3
2
1
0
stop_disable POR
wait_disable 0 0
COPR EXTR
FIELD FIELD FIELD FIELD 0 0 0 1 PWMA 1 PWMA 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 0 0 1
0 0 0 0 0
CAN CAN 0 0 0
$8
SIM_PUDR W SIM_ CLKOSR R W R W
EMI_ RESET MODE EMI_ RESET MODE 0 0 0 0 0 0
IRQ IRQ 0 0 0
XBOOT PWMB
PWMA DATA 0
CTRL CTRL CLKDI S CLKDI S
ADR ADR
JTAG TMRD TMRC TMRA JTAG TMRD TMRC TMRA CLKOSEL CLKOSEL
PWMA XBOOT PWMB DATA 0 A23 A23 0 A22 A22 0 A21 A21 A20 A20
$9
$10
SIM_GPS
TC0_ TC1_A MISO_ ALT LT ALT
SS_ ALT
PWM5 PWM4 PWM3 PWM2 _ALT _ALT _ALT _ALT
$11 $12 $13
SIM_PCE SIM_ISALH SIM_ISALL
R W R W R W R W
EMI 1
ADC B ADC A 1 1
CAN 1
DEC 1 DEC 0 TMRD TMRC TMRB TMRA SCI 1 1 1 1 1 1 1 1
SCI 0 1
SPI 1 1
SPI 0 1
PWM B
PWM A
ISAL[23:22]
ISAL[21:6]
0
= Read as 0 = Reserved
Figure 6-2 SIM Register Map Summary
6.5.1
Base + $0 Read Write RESET
SIM Control Register (SIM_CONTROL)
15
0
14
0
13
O
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
Once Ebl0 0
4
SW RST 0
3
2
1
0
stop_disable 0 0
wait_disable 0 0
0
0
0
0
0
0
0
0
0
0
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1
Reserved--Bits 15-6
This bit field is reserved or not implemented. It is read as zero and cannot be modified by writing.
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6.5.1.2
* *
OnCE Enable (OnCE EBL)--Bit 5
0 = OnCE clock to 56800E core enabled when core TAP is enabled 1 = OnCE clock to 56800E core is always enabled
6.5.1.3 6.5.1.4
* * * *
Software Reset (SW RST)--Bit 4 Stop Disable (STOP_DISABLE)--Bits 3-2
Writing 1 to this field will cause the part to reset.
00 = Stop mode will be entered when the 56800E core executes a STOP instruction 01 = The 56800E STOP instruction will not cause entry into Stop mode; stop_disable can be reprogrammed in the future 10 = The 56800E STOP instruction will not cause entry into Stop mode; stop_disable can then only be changed by resetting the device 11 = Same operation as 10
6.5.1.5
* * * *
Wait Disable (WAIT_DISABLE)--Bits 1-0
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction 01 = The 56800E WAIT instruction will not cause entry into Wait mode; wait_disable can be reprogrammed in the future 10 = The 56800E WAIT instruction will not cause entry into Wait mode; wait_disable can then only be changed by resetting the device 11 = Same operation as 10
6.5.2
SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Software should only clear this register.
Base + $1 Read Write RESET
0 0 0 0 0 0 0 0 0 0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
SWR
4
COPR
3
EXTR
2
POR
1
0
0
0
0
0
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
6.5.2.1 6.5.2.2
Reserved--Bits 15-6 Software Reset (SWR)--Bit 5
This bit field is reserved or not implemented. It is read as zero and cannot be modified by writing.
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SWRST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
6.5.2.3
COP Reset (COPR)--Bit 4
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
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6.5.2.4
External Reset (EXTR)--Bit 3
If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit while writing a 1 to the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET pin being asserted low.
6.5.2.5
Power-On Reset (POR)--Bit 2
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can only be cleared by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On Reset.
6.5.2.6
Reserved--Bits 1-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.3
SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3)
Only SIM_SCR0 is shown in this section. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality.
Base + $2 Read Write POR
15
14
13
12
11
10
9
8
FIELD
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
6.5.3.1
Software Control Data 1 (FIELD)--Bits 15-0
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by software developers to contain data that will be unaffected by the other reset sources (reset pin, software reset, and COP reset).
6.5.4
Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F4.
Base + $6 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
1
6
1
5
1
4
1
3
0
2
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
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Register Descriptions
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $001D.
Base + $7 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Base + $8 Read Write RESET
15
0
14
0
13
0
12
0
11
RESET 0
10
IRQ 0
9
0
8
0
7
0
6
0
5
0
4
0
3
JTAG 0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1 6.5.6.2 6.5.6.3
RESET IRQ JTAG
This bit controls the pull-up resistors on the RESET pin.
This bit controls the pull-up resistors on the IRQA pin.
This bit controls the pull-up resistors on the TRST, TMS and TDI pins.
6.5.7
CLKO Select Register (SIM_CLKOSR)
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are for test purposes only, and are subject to significant unspecified latencies at high frequencies. The upper four bits of the GPIOB register can function as GPIO, Quad Decoder #0 signals, or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed to operate as peripheral outputs, then the choice between Quad Decoder #0 and additional clock outputs is made here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as Quad Decoder #0. This can be changed by altering PHASE0 through INDEX below. The CLKOUT pin is not bonded out in the 56F8322. Instead, it is offered only as a pad for die-level testing.
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Base + $A Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
CLK DIS 1
4
3
2
CLKOSEL
1
0
PHSA PHSB INDEX HOME 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
6.5.7.1 6.5.7.2
* *
Reserved--Bits 15-10 PHASEA0 (PHSA)--Bit 9
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
0 = Peripheral output function of GPIO B[7] is defined to be PHASEA0 1 = Peripheral output function of GPIO B[7] is defined to be the oscillator clock (MSTR_OSC, see Figure 3-4)
6.5.7.3
* *
PHASEB0 (PHSB)--Bit 8
0 = Peripheral output function of GPIO B[6] is defined to be PHASEB0 1 = Peripheral output function of GPIO B[6] is defined to be SYS_CLK_X2
6.5.7.4
* *
INDEX0 (INDEX)--Bit 7
0 = Peripheral output function of GPIO B[5] is defined to be INDEX0 1 = Peripheral output function of GPIO B[5] is defined to be SYS_CLK
6.5.7.5
* *
HOME0 (HOME)--Bit 6
0 = Peripheral output function of GPIO B[4] is defined to be HOME0 1 = Peripheral output function of GPIO B[4] is defined to be the prescaler clock (FREF, see Figure 3-4)
6.5.7.6
* *
Clockout Disable (CLKDIS)--Bit 5
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL 1 = CLKOUT is tri-stated
6.5.7.7
* * * * * * * * * *
CLockout Select (CLKOSEL)--Bits 4-0
Selects clock to be muxed out on the CLKO pin. 00000 = SYS_CLK (from ROCS - DEFAULT) 00001 = Reserved for factory test--56800E clock 00010 = Reserved for factory test--XRAM clock 00011 = Reserved for factory test--PFLASH odd clock 00100 = Reserved for factory test--PFLASH even clock 00101 = Reserved for factory test--BFLASH clock 00110 = Reserved for factory test--DFLASH clock 00111 = MSTR_OSC Oscillator output 01000 = Fout (from OCCS) 01001 = Reserved for factory test--IPB clock
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Register Descriptions
* * * * * * *
01010 = Reserved for factory test--Feedback (from OCCS, this is path to PLL) 01011 = Reserved for factory test--Prescaler Clk (from OCCS) 01100 = Reserved for factory test--Postscaler Clk (from OCCS) 01101 = Reserved for factory test--SYS_CLK_x2 (from OCCS) 01110 = Reserved for factory test--SYS_CLK_DIV2 01111 = Reserved for factory test--SYS_CLK_D 10000 = ADCA Clk
6.5.8
SIM GPIO Peripheral Select Register (SIM_GPS)
All of the peripheral pins on the 56F8322 share their I/O with GPIO ports. To select peripheral or GPIO control, program the GPIOx_PER register. When SPI 0 and SCI 1, Quad Timer C and SCI 1, or PWMA and SPI 1 are multiplexed, there are two possible peripherals as well as the GPIO functionality available for control of the I/O. The SIM_GPS register is used to determine which peripheral has control. The default peripherals are SPI 0, Quad Timer C, and PWMA. As shown in Figure 6-10, the GPIO has the final control over which pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O.
GPIOX_PER Register
GPIO Controlled
0 I/O Pad Control 1
SIM_GPS Register Quad Timer Controlled 0
SCI Controlled
1
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
Base + $B Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
C6 0
6
C5 0
5
B1 0
4
B0 0
3
A5 0
2
A4 0
1
A3 0
0
A2 0
0
0
0
0
0
0
0
0
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
6.5.8.1
Reserved--Bits 15-8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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6.5.8.2
* *
GPIO C6 (C6)--Bit 7
This bit selects the alternate function for GPIO C6. 0 = TC0 (default) 1 = TXD0
6.5.8.3
* *
GPIO C5 (C5)--Bit 6
This bit selects the alternate function for GPIO C5. 0 = TC1 (default) 1 = RXD0
6.5.8.4
* *
GPIO B1 (B1)--Bit 5
This bit selects the alternate function for GPIO B1. 0 = MISO0 (default) 1 = RXD1
6.5.8.5
* *
GPIO B0 (B0)--Bit 4
This bit selects the alternate function for GPIO B0. 0 = SS0 (default) 1 = TXD1
6.5.8.6
* *
GPIO A5 (A5)--Bit 3
This bit selects the alternate function for GPIO A5. 0 = PWMA5 1 = SCLK1
6.5.8.7
* *
GPIO A4 (A4)--Bit 2
This bit selects the alternate function for GPIO A4. 0 = PWMA4 1 = MOS1
6.5.8.8
* *
GPIO A3 (A3)--Bit 1
This bit selects the alternate function for GPIO A3. 0 = PWMA3 1 = MISO1
6.5.8.9
* *
GPIO A2 (A2)--Bit 0
This bit selects the alternate function for GPIO A2. 0 = PWMA2 1 = SS1
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Register Descriptions
6.5.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip.
Base + $C Read Write RESET
1 1
15
1
14
1
13
ADCA 1
12
CAN 1
11
1
10
DEC0 1
9
1
8
TMRC 1
7
1
6
5
4
3
SPI1 1
2
SPI0 1
1
1
0
PWMA 1
TMRA SCI 1 SCI 0 1 1 1
1
1
1
1
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
6.5.9.1 6.5.9.2
* *
Reserved--Bits 15-14 Analog-to-Digital Converter A Enable (ADCA)--Bit 13
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3
* *
FlexCAN Enable (CAN)--Bit 12
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4 6.5.9.5
* *
Reserved--Bits 11 Decoder 0 Enable (DEC0)--Bit 10
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.6 6.5.9.7
* *
Reserved--Bits 9 Quad Timer C Enable (TMRC)--Bit 8
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.8
Reserved--Bits 7
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
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6.5.9.9
* *
Quad Timer A Enable (TMRA)--Bit 6
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.10
* *
Serial Communications Interface 1 Enable (SCI1)--Bit 5
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.11
* *
Serial Communications Interface 0 Enable (SCI0)--Bit 4
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12
* *
Serial Peripheral Interface 1 Enable (SPI1)--Bit 3
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.13
* *
Serial Peripheral Interface 0 Enable (SPI0)--Bit 2
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.14 6.5.9.15
* *
Reserved--Bit 1 Pulse Width Modulator A Enable (PWMA)--Bit 0
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.10
I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower six bits of address and the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-13. Note: If this register is set to something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected.
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Register Descriptions
"Hard Coded" Address Portion
Instruction Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
2 bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
Figure 6-13 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISAL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt. Note: Note: The default value of this register set points to the EOnCE registers. The pipeline delay between setting this register set and using short I/O addressing with the new value is five cycles.
Base + $D Read Write RESET
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISAL[23:22] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1
Input/Output Short Address Low (ISAL[23:22])--Bit 1-0
This field represents the upper two address bits of the "hard coded" I/O short address.
Base + $E Read Write RESET
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISAL[21:6] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)
6.5.10.2
Input/Output Short Address Low (ISAL[21:6])--Bit 15-0
This field represents the lower 16 address bits of the "hard coded" I/O short address.
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6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120Mhz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60Mhz. The SIM provides power modes (STOP, WAIT) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible means to manage power consumption. Power utilization can be minimized in several ways. In the OCCS, the relaxation oscillator, crystal oscillator, and PLL may be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused. Clock enables provide the means to disable individual clocks. Some peripherals provide further controls to disable unused sub-functions. Refer to the Part 3 On-Chip Clock Synthesis (OCCS) and the 56F8300 Peripheral User Manual for further details. The memory, peripheral and core clocks all operate at the same frequency (60MHz max).
6.7 Power-Down Modes
The 56F8322 operates in one of three power-down modes, as shown in Table 6-2.
Table 6-2 Clock Operation in Power-Down Modes
Mode Run Wait Core Clocks Active Core and memory clocks disabled Peripheral Clocks Active Active Description Device is fully functional Peripherals are active and can produce interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications. The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts (IRQA) 3. COP reset 4. External reset 5. Power-on reset
Stop
System clocks continue to be generated in the SIM, but most are gated prior to reaching memory, core and peripherals.
All peripherals, except the COP/watchdog timer, run off the IPbus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz. Refer to the PCE register in Section 6.5.9 and ADC power modes. Power is a function of the system frequency which can be controlled through the OCCS.
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Stop and Wait Mode Disable Function
6.8 Stop and Wait Mode Disable Function
Permanent Disable
D
Q
D-FLOP
C
56800E
Reprogrammable Disable
STOP_DIS D Q D-FLOP
Clock Select
C
R Note: Wait disable circuit is similar
RESET
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. The peripheral bus continues to run in Wait mode, but not in Stop mode. The PLL must be explicitly shut down prior to entering Stop mode, if desired. When the PLL is shut down, the 56800E system clock must be set equal to the prescaler output. Some applications require the 56800E STOP/WAIT instructions be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL) described in Section 6.5.1. This procedure can be on either a permanent or temporary basis. Permanently assigned applications last only until their next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within the SIM itself, by writing to the SIM_CONTROL register and the COP reset. Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced to permit proper operation of the device. A POR reset is first extended for 64 clock cycles to permit stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated. It is then followed by a 32 clock window in which peripherals are released to implement flash security, and, finally, followed by a 32 clock window in which the core is initialized. After completion of the described reset sequence, application code will begin execution. Resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock.
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Part 7 Security Features
The 56F8322 offers security features intended to prevent unauthorized users from reading the contents of the FM array. The 56F8322's Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array. However, part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program, as this code would defeat the purpose of security. At the same time, the user may also wish to put a "backdoor" in his program. As an example, the user downloads a security key through the SCI, allowing access to a programming routine that updates parameters stored in another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the 56F8322 can be secured by programming the security bytes located in the FM configuration field, which occupies a portion of the FM array. These non-volatile bytes will keep the part secured through reset and through power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory chapter in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification, the 56F8322 will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8322 has several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Blocking these are outlined in the next subsections.
7.2.1
Forced Operating Mode Selection
At boot time, the SIM determines in which functional modes the 56F8322 will operate. These are: * Unsecured Mode * Secure Mode (EOnCE disabled) When Flash security is enabled as described in the Flash Memory module specification, the 56F8322 will disable the EOnCE debug interface.
7.2.2
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the 56F8322 boots, the chip level JTAG TAP (Test Access Port) is active and provides the chip's boundary scan capability and access to the ID register. Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled. The 56800E core has an input which disables reading of internal memory via the EOnCE/JTAG. The FM sets this input at reset to a value determined by the contents of the FM security bytes.
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Flash Access Blocking Mechanisms
7.2.3
Flash LOCKOUT_RECOVERY
If a user inadvertently enables security on the 56F8322, a lockout recovery mechanism is provided which allows the complete erasure of the internal Flash contents, including the configuration field, and thus disables security (the protection register is cleared). This does not compromise security, as the entire contents of the user's secured code stored in Flash gets erased before security is disabled on the 56F8322 on the next reset or power-up sequence. To start the lockout recovery sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller's instruction register. The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to control the clock divider circuit within the FM module. This divider, FMCLKDIV[6:0], is used to control the period of the clock used for timed events in the FM erase algorithm. This register must be set with appropriate values before the lockout sequence can begin. Refer to the 56F8300 Peripheral User Manual for more details on setting this register value. The value of the JTAG FMCLKDIV[6:0] will replace the value of the FM register FMCLKD that divides down the system clock for timed events, as illustrated in Figure 7-1. FMCLKDIV[6] will map to the PRDIV8 bit, and FMCLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The "Writing the FMCLKD Register" section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values.
Flash Memory system_clk 2 input clock 7 FMCLKD 7
DIVIDER
FMCLKDIV JTAG FMERASE
7
Figure 7-1 JTAG to FM Connection for LOCKOUT_RECOVERY
Two examples of FMCLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8=FMCLKDIV[6]=0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This translates into an FMCLKDIV[6:0] value of $13 or $14, respectively.
150[kHz]
( <
system_clk (2) (DIV + 1)
)<
200[kHz]
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EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8=FMCLKDIV[6]=1.Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of 181kHz. This translates to an FMCLKDIV[6:0] value of $49 or $4A, respectively.
150[kHz]
( <
system_clk (2)(8) (DIV + 1)
)<
200[kHz]
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User Manual. Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the 56F8322 (by asserting external chip reset) to return to normal unsecured operation.
7.2.4
Product Analysis
The recommended method of unsecuring a programmed 56F8322 for product analysis of field failures is via the backdoor key access. The customer would need to supply Motorola with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set. An alternative method for performing analysis on a secured microcontroller would be to mass-erase and reprogram the Flash with the original code, but modify the security bytes. To insure that a customer does not inadvertently lock himself out of the 56F8322 during programming, it is recommended that he program the backdoor access key first, his application code second and the security bytes within the FM configuration field last.
Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. Any information contained here supercedes the generic information in the 56F8300 Peripheral User Manual.
8.2 Configuration
There are three GPIO ports defined on the 56F8322. The width of each port and the associated peripheral function is shown in Table 8-3. The specific mapping of GPIO port pins is shown in Table 8-2.
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Configuration
Table 8-1 GPIO Ports Configuration
GPIO Port Port Width 12 8 7 Available Pins in 56F8322 7 8 6 PWM SPI 0, DEC 0 XTAL, EXTAL, CAN, TMRC Peripheral Function Reset Function
A B C
PWM SPI 0, DEC 0 XTAL, EXTAL, CAN, TMRC
Table 8-2 GPIO External Signals Map
Peripheral Function
PWMA0 PWMA1 PWMA2/SSI PWMA3/MISO1 PWMA4/MOSI1 PWMA5/SCLK1 FaultA0 FaultA1 FaultA2 ISA0 ISA1 ISA2 SS0/TXD1 MISO0/RXD1 MOSI0 SCLK0 HOME0/TA3 INDEX0/TA2
GPIO Function
GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 GPIOA8 GPIOA9 GPIOA10 GPIOA11 GPIOB0 GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5
Notes
SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis
SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis
Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A
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Table 8-2 GPIO External Signals Map (Continued)
Peripheral Function
PHASEB0/TA1 PHASEA0/TA0 EXTAL XTAL CAN_RX CAN_TX TC3 TC1/RXD0 TC0/TXD0
GPIO Function
GPIOB6 GPIOB7 GPIOC0 GPIOC1 GPIOC2 GPIOC3 GPIOC4 GPIOC5 GPIOC6
Notes Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A Pull-ups should default to disabled Pull-ups should default to disabled
SIM register SIM_GPS is used to select between Timer C and SCI0 on a pin-by-pin basis SIM register SIM_GPS is used to select between Timer C and SCI0 on a pin-by-pin basis
Note: Shaded rows are not available in this package.
8.3 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and GPIOx_PER registers change from chip to chip. Tables 4-21 through 4-23 define the actual reset values of these registers for the 56F8322.
Part 9 Joint Test Action Group (JTAG)
9.1 56F8322 Information
Please contact your Motorola sales representative or authorized distributor for device/package-specific BSDL information.
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General Characteristics
Part 10 Specifications
10.1 General Characteristics
The 56F8322 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term "5V-tolerant" refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Note: All specification meet both Automotive and Industrial requirements unless individual specifications are listed.
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
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Table 10-1 Absolute Maximum Ratings
(VSS = VSSA_ADC = 0) Characteristic Supply voltage ADC Supply Voltage Symbol VDD_IO VDDA_ADC, VREFH VDDA_OSC_PLL VDDA_CORE VIN VINA VOUT VOD TA TA TJ TJ TSTG TSTG
OCR_DIS is High Pin Groups 1, 3, 4, 5 Pin Group 7 Pin Groups 1, 2, 3 GPIO pins used in open drain mode
Notes
Min - 0.3
Max 4.0 4.0
Unit V V
VREFH must be
less than or equal to VDDA_ADC
- 0.3
Oscillator/PLL Supply Voltage Internal Logic Core Supply Voltage Input Voltage (digital) Input Voltage (analog) Output Voltage Output Voltage (open drain) Ambient Temperature (Automotive) Ambient Temperature (Industrial) Junction Temperature (Automotive) Junction Temperature (Industrial) Storage Temperature (Automotive) Storage Temperature (Industrial)
- 0.3 - 0.3 -0.3 -0.3 -0.3 -0.3 -40 -40 -40 -40 -55 -55
4.0 3.0 6.0 4.0 4.0 6.0 125 105 150 125 150 150
V V V V V V C C C C C C
Pin Group 1: TC0-1, FAULTA0, SS0, MISO0, MOSI0, SCLK0, HOME0, INDEX0, PHASEA0, PHASEB0, CAN_RX, CAN_TX Pin Group 2: TDO Pin Group 3: PWMA0-5 Pin Group 4: RESET, TMS, TDI, IRQA Pin Group 5: TCK Pin Group 6: XTAL, EXTAL Pin Group 7: ANA0-6
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General Characteristics
Although the 56F8322 is specified to operate correctly over the full -40C to 125C ambient temperature range, it is assumed not to be at the extremes of this range 100% of the time.
Table 10-2 Junction Temperature Profile
Temperature 40C 80C 110C 125C 150C Total Hours of Operation 99,000 27,000 5,400 2,700 900 135,000
10.1.1
ElectroStatic Discharge Model
Table 10-3 56F8322 ESD Protection
Characteristic Min 2000 200 500 Typ -- -- -- Max -- -- -- Unit V V V
ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM)
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Table 10-4 Thermal Characteristics6
Characteristic Junction to ambient Natural Convection Junction to ambient (@1m/sec) Junction to ambient Natural Convection Junction to ambient (@1m/sec) Four layer board (2s2p) Four layer board (2s2p)
Comments
Symbol RJA RJMA RJMA (2s2p) RJMA RJB RJC JT
P I/O PD
Value 41 34 34
Unit C/W C/W C/W
Notes 2 2 1,2
29
C/W
1,2
Junction to board Junction to case Junction to center of case I/O pin power dissipation Power dissipation
24 8 2 User Determined P D = (IDD x VDD + P I/O) (TJ - TA) /JA
C/W C/W C/W W W
4 3 5
Junction to center of case Notes: 1. 2.
PDMAX
C
3.
4. 5.
6.
Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. Junction to ambient thermal resistance, Theta-JA (RqJA ), was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p, where "s" is the number of signal layers and "p" is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. Junction to case thermal resistance, Theta-JC (RqJC ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. Junction to board thermal resistance, Theta-JB (RqJB ), is a metric of the thermal resistance from the junction to the printed circuit board determined per JESD51-8. Thermal Characterization Parameter, Psi-JT (YJT ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. YJT is a useful value to use to estimate junction temperature in steady-state customer environments. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
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General Characteristics
Table 10-5 Recommended Operating Conditions
(VREFLO= 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL )
Characteristic Supply voltage ADC Supply Voltage Symbol
VDD_IO VDDA_ADC, VREFH VDDA_OSC
_PLL
Notes
Min 3
Typ 3.3 3.3
Max 3.6 3.6
Unit
V V
VREFH must be less than or equal to VDDA_ADC
3
Oscillator/PLL Supply Voltage Internal Logic Core Supply Voltage Device Clock Frequency Input High Voltage (digital) Input High Voltage (XTAL/EXTAL,
XTAL is not driven by an external clock)
3
OCR_DIS is High
3.3 2.5 -- -- --
3.6 2.75 60 5.5 VDDA+0.3
V V MHz V V
VDD_CORE FSYSCLK VIN VIHC
2.25 0
Pin Groups 1, 3 ,4, 5 Pin Group 6
2 VDDA-0.8
Input high voltage (XTAL/EXTAL,
XTAL is driven by an external clock)
VIHC VIL IOH
Pin Group 6 Pin Groups 1, 3, 4, 5, 6 Pin Groups 1, 2 Pin Group 3
2 -0.3
-- -- -- -- -- --
VDDA+0.3 0.8 -4 -12 4 12
125 (RJA X PD) 105 (RJA X PD)
V V mA
Input Low Voltage Output High Source Current1 VOH = 2.4V (VOH min.) Output Low Sink Current1 VOL = 0.4V (VOL max) Ambient Operating Temperature (Automotive) Ambient Operating Temperature (Industrial) Flash Endurance (Automotive) (Program Erase Cycles) Flash Endurance (Industrial) (Program Erase Cycles) Flash Data Retention
IOL
Pin Groups 1, 2 Pin Group 3
mA
TA TA NF NF TR
TA = -40C to 125C TA = -40C to 105C TJ <= 70C avg
-40 -40 10,000 10,000 15
-- -- -- -- --
C C Cycles Cycles Years
-- -- --
Note 1. Total chip source or sink current cannot exceed 150mA Pin Group 1: TC0-1, FAULTA0, SS0, MISO0, MOSI0, SCLK0, HOME0, INDEX0, PHASEA0, PHASEB0, CAN_RX, CAN_TX Pin Group 2: TDO Pin Group 3: PWMA0-5 Pin Group 4: RESET, TMS, TDI, IRQA Pin Group 5: TCK Pin Group 6: XTAL, EXTAL Pin Group 7: ANA0-6
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10.2 DC Electrical Characteristics
Table 10-6 DC Electrical Characteristics
Over Recommended Operating Conditions, VDDA = VDDA_ADC,_VDDA_OSC_PLL Characteristic Output High Voltage Output Low Voltage Digital Input Current High pull-up enabled or disabled Digital Input Current High
with pull-down
Symbol
VOH VOL IIH IIH IIHADC IIL IIL IIL IILADC IEXTAL IXTAL
Notes
Min 2.4 --
Typ -- -- 0 80 0 -100 0 0 0 0 0 -- 0 0.3 4.5 5.5 6 6
Max -- 0.4 +/- 2.5 160 +/- 3.5 -200 +/- 2.5 +/- 2.5 +/- 3.5 +/- 2.5 +/- 2.5 200 +/- 2.5 -- -- -- -- --
Unit
V V
A A A A A A A A A A A
Test Conditions
IOH =IOHmax IOL =IOLmax VIN = 3.0V to 5.5V VIN = 3.0V to 5.5V VIN = VDDA VIN = 0V VIN = 0V VIN = 0V VIN = 0V VIN = VDDA or 0V VIN = VDDA or 0V VIN = VDDA or 0V VOUT = 3.0V to 5.5V or 0V
Pin Groups 1, 3, 4 Pin Group5
-- 40 -- -50 -- -- -- --
ADC Input Current High Digital Input Current Low
pull-up enabled
Pin Group 7 Pin Groups 1, 3, 4 Pin Groups 1, 3, 4 Pin Group 5
Digital Input Current Low
pull-up disabled
Digital Input Current Low
with pull-down
ADC Input Current Low EXTAL Input Current Low
clock input
Pin Group 7
XTAL Input Current Low
clock input
CKLMODE = High CKLMODE = Low
-- -- -- -- -- -- -- --
Output Current High Impedance State Schmitt Trigger Input Hysteresis Input Capacitance (EXTAL/XTAL) Output Capacitance (EXTAL/XTAL) Input Capacitance Output Capacitance See Pin Groups in Table 10-5
IOZ VHYS CINC COUTC CIN COUT
Pin Groups 1, 2, 3 Pin Groups 1, 3, 4, 5
V
pF
pF
pF pF
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DC Electrical Characteristics
Table 10-7 Power-On Reset Low Voltage Parameters
Characteristic POR Trip Point LVI, 2.5V Supply, trip point1 LVI, 3.3V supply, trip point2 Bias Current Symbol POR VEI2.5 VEI3.3 Min 1.75 2.05 2.6 Typ 1.8 2.14 2.7 110 Max 1.9 2.25 2.8 130 Units V V V uA
I bias
1. When VDD drops below VEI2.5, an interrupt is generated. 2. When VDD drops below VEI3.3, an interrupt is generated.
Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
Mode RUN1_MAC IDD_IO1 115mA IDD_ADC 25mA IDD_OSC_PLL 2.5mA Test Conditions * 60MHz Device Clock * All peripheral clocks are enabled * Continuous MAC instructions with fetches from Data RAM * ADC powered on and clocked Wait3 60mA 0uA 2.5mA * 60MHz Device Clock * All peripheral clocks are enabled * ADC powered off Stop1 5.7mA 0uA 450uA * 4MHz Device Clock * All peripheral clocks are off * ADC powered off * PLL powered off Stop2 5mA 0uA 150uA * Relaxation oscillator is off * All peripheral clocks are off * ADC powered off * PLL powered off
1. No Output Switching (Output switching current can be estimated from I = CVf for each output)
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Table 10-9 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
Mode RUN1_MAC IDD_Core 110mA IDD_IO1 13A IDD_ADC 25mA IDD_OSC_PLL 2.5mA Test Conditions * 60MHz Device Clock * All peripheral clocks are enabled * Continuous MAC instructions with fetches from Data RAM * ADC powered on and clocked Wait3 55mA 13A 0A 2.5mA * 60MHz Device Clock * All peripheral clocks are enabled * ADC powered off Stop1 700A 13uA 0A 360uA * 4MHz Device Clock * All peripheral clocks are off * ADC powered off * PLL powered off Stop2 100A 13A 0A 150A * Relaxation oscillator is off * All peripheral clocks are off * ADC powered off * PLL powered off
1. No Output Switching
10.2.1
Voltage Regulator Specifications
The 56F8322 has two on-chip regulators. One supplies the PLL. It has no external pins and therefore has no external characteristics which must be guaranteed (other than proper operation of the device). The second regulator supplies approximately 2.6V to the 56F8322's core logic. This regulator requires two external 2.2F, or greater, capacitors for proper operation. Ceramic and tantalum capacitors tend to provide better performance tolerances. The output voltage can be measured directly on the VCAP pins The specifications for this regulator are shown in Table 10-7.
Table 10-10. Regulator Parameters
Characteristic Un-Loaded Output Voltage (0mA Load) Loaded Output Voltage (250mA load) Line Regulation @ 250mA load (VDD33 ranges from 3.0V to 3.6V) Short Circuit Current ( output shorted to ground) Bias Current Power-down Current Short-Circuit Tolerance (output shorted to ground) Symbol VRNL VRL VR Iss I bias Ipd TRSC Min 2.25 2.25 2.25 -- -- -- 30 Typical -- -- -- -- 5.8 0 -- Max 2.75 2.75 2.75 700 7 2 -- Unit V V V mA mA A minutes
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AC Electrical Characteristics
Table 10-11. PLL Parameters
Characteristics PLL Startup time Resonator Startup time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode Symbol TPS TRS TPV TPJ IBIAS IPD Min 0.3 0.1 120 -- -- -- Typical 0.5 0.18 -- -- 1.5 100 Max 10 1 200 175 2 150 Unit ms ms ps ps mA A
10.2.2
Temperature Sense
Table 10-12 Temperature Sense Parametrics
Characteristics Symbol K VDDA IDD-OFF IDD-ON TACC RES Min 7 3.0 -- -- -2 -- Typical 7.2 3.3 -- -- -- -- Max -- 3.6 10 250 +2 1 Unit mV/C V A A C C / bit2
K-factor1 Supply Voltage Supply Current - OFF Supply Current - ON Accuracy Resolution
1. This is the inverse of the parameter "m" in Figure 14-1 of the 56F8300 Peripheral User Manual. 2. Assuming a 10-bit range from 0V to 3.6V.
10.3 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 10-6. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 10-1.
VIH Input Signal Midpoint1 Fall Time
Note: The midpoint is VIL + (VIH - VIL)/2.
Low
High
90% 50% 10%
VIL
Rise Time
Figure 10-1 Input Signal Measurement References
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Figure 10-2 shows the definitions of the following signal states: * * * * Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data Active Data3 Valid Data3
Figure 10-2 Signal States
10.4 Flash Memory Characteristics
Table 10-13 Flash Timing Parameters
Characteristic Program time 1, 2 Erase time3, 4 Mass erase time5 Symbol Min 20 20 100 Typ -- -- -- Max -- -- -- Unit us ms ms
Tprog Terase Tme
1. Program specification guaranteed from TA = 0C to 85C 2. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Program Flash Module, as it contains two interleaved memories. 3. Erase specification guaranteed from TA = 0C to 85C 4. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash Module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes. 5. Mass erase specification guaranteed from TA = 0C to 85C
10.5 External Clock Operation Timing
Table 10-14 External Clock Operation Timing Requirements1
Characteristic Frequency of operation (external clock driver)2 Clock Pulse Width3 External clock input rise time4 External clock input fall time5
1. Parameters listed are guaranteed by design. 2. See Figure 10-3 for details on using the recommended connection of an external clock driver.
Symbol fosc tPW trise tfall
Min 0 2.0 -- --
Typ -- -- -- --
Max 240 -- 10 10
Unit MHz ns ns ns
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Phase Locked Loop Timing
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function. 4. External clock input rise time is measured from 10% to 90%. 5. External clock input fall time is measured from 90% to 10%.
VIH
External Clock
90% 50% 10%
90% 50% 10%
tPW Note: The midpoint is VIL + (VIH - VIL)/2.
tPW
tfall
trise
VIL
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-15 PLL Timing
Characteristic External reference crystal frequency for the PLL1 PLL output frequency2 (fOUT/2) PLL stabilization time3 0 to +85C Symbol fosc fop tplls Min 4 160 -- Typ 8 -- 1 Max 8 260 10 Unit MHz MHz ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT)/2, please refer to the OCCS chapter in the 56F8300 Peripheral User Manual. 3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
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10.7 Oscillator Parameters
Table 10-16 Crystal Oscillator Parameters
Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Bias Current, high-drive mode Bias Current, low-drive mode Quiescent Current, power-down mode Symbol TCS TRS RESR TD TPV TRJ TRP IBIASH IBIASL IPD Min 4 0.1 -- 70 0.12 -- -- -- -- -- Typ 5 0.18 -- -- -- -- -- 250 80 0 Max 10 1 120 250 1.5 300 300 290 110 1 Unit ms ms ohms ps ns ps ps A A A
Table 10-17 Relaxation Oscillator Parameters
Characteristic Center Frequency Minimum Tuning Step Size (See Note) Maximum Tuning Step Size (See Note) Frequency Accuracy -50C to +150C (See Figure 10-4) Maximum Cycle to Cycle Jitter Stabilization Time from Power-up Note: Symbol Min -- -- Typ 8 82 Max -- -- Units MHz ps
--
41
--
ns
--
+/- 1.78
+/- 2.0
%
--
--
500
ps
--
--
4
s
An LSB change in the tuning code results in an 82ps shift in the frequency period, while an MSB change in the tuning code results in a 41ns shift in the frequency period.
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
8.2 Typical Response 8.1
8.0 Freq in MHz
7.9
7.8
7.7
7.6
7.5 - 50 - 30 - 10 + 10 + 30 + 50 Temp + 70 + 90 + 110 + 130 + 150
Figure 10-4 Frequency versus Temperature
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All the address and data buses described here are internal.
Table 10-18 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
Characteristic Minimum RESET Assertion Duration Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Width Assertion to Recover from Stop State3 Symbol tRA tIRW tIG tIG - FAST tIW Typical Min 16T 1.5T TBD TBD 1.5T Typical Max -- -- TBD TBD -- ns Figure 10-8 Unit ns ns ns See Figure Figure 10-5 Figure 10-6 Figure 10-7
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop modes), T = 125ns. 2. Parameters listed are guaranteed by design. 3. The interrupt instruction fetch is visible on the pins only in Mode 3.
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RESET
tRAZ tRA tRDA
PAB PDB
First Fetch
Figure 10-5 Asynchronous Reset Timing
IRQA
tIRW
Figure 10-6 External Interrupt Timing (Negative-Edge-Sensitive)
PAB First Interrupt Instruction Execution
tIDM
IRQA
a) First Interrupt Instruction Execution General Purpose I/O Pin
tIG IRQA
b) General Purpose I/O
Figure 10-7 External Level-Sensitive Interrupt Timing
tIW
IRQA
tIF
PAB
First Instruction Fetch Not IRQA Interrupt Vector
Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing
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Serial Peripheral Interface (SPI) Timing
10.9 Serial Peripheral Interface (SPI) Timing
Table 10-19 SPI Timing1
Operating Conditions: VSS = VSSA_ADC = 0V, VDD_IO = VDDA_ADC = 3.0-3.6V, TA = -40 to +125C, CL 50pF, fop = 60MHz Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave
1. Parameters listed are guaranteed by design.
Symbol tC
Min
Max
Unit
See Figure 10-9, 10-10, 10-11, 10-12
33.33 33.33 tELD -- 16.67 tELG -- 66.67 tCH 16 16.67 tCL 16 16.67 tDS 20 0 tDH 0 2 tA 4.8
-- --
ns ns
10-12 -- -- ns ns 10-12 -- -- ns ns 10-9, 10-10, 10-11, 10-12
-- --
ns ns
10-12 -- -- ns ns 10-9, 10-10, 10-11, 10-12
-- --
ns ns
-- --
ns ns
10-9, 10-10, 10-11, 10-12
10-12 15 ns
tD 3.7 tDV -- -- tDI 0 0 tR -- -- tF -- -- 9.7 9.0 ns ns 11.5 10.0 ns ns -- -- ns ns 4.5 20.4 ns ns 15.2 ns
10-12
10-9, 10-10, 10-11, 10-12
10-9, 10-10, 10-11, 10-12
10-9, 10-10, 10-11, 10-12
10-9, 10-10, 10-11, 10-12
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1
SS
(Input)
SS is held High on master
tC tR tCL tCH tF tR tF
SCLK (CPOL = 0) (Output)
SCLK (CPOL = 1) (Output)
tDH tDS
tCL
tCH
MISO (Input)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14-1
Master LSB out
tR
Figure 10-9 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC tCL tF tR
SCLK (CPOL = 0) (Output)
tCH
tF
SCLK (CPOL = 1) (Output)
tCL tCH tR tDS tDH
MISO (Input)
tDV(ref)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14- 1
Master LSB out
tR
Figure 10-10 SPI Master Timing (CPHA = 1)
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Serial Peripheral Interface (SPI) Timing
SS
(Input)
tC tCL tF tR tELG
SCLK (CPOL = 0) (Input)
tELD
tCH tCL
SCLK (CPOL = 1) (Input)
tA tCH tR tF tD
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 10-11 SPI Slave Timing (CPHA = 0)
SS
(Input)
tC tF tCL tCH tELD tCL tR
SCLK (CPOL = 0) (Input)
tELG
SCLK (CPOL = 1) (Input)
tDV tA
tCH tF
tR tD
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 10-12 SPI Slave Timing (CPHA = 1)
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10.10 Quad Timer Timing
Table 10-20 Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0V, VDD_IO = VDDA_ADC = 3.0-3.6V, TA = -40 to +125C, CL 50pF Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period Symbol PIN PINHL POUT POUTHL Min 2T + 6 1T + 3 1T - 3 0.5T - 3 Max -- -- -- -- Unit ns ns ns ns See Figure 10-13 10-13 10-13 10-13
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design.
Timer Inputs
PIN PINHL PINHL
Timer Outputs
POUT POUTHL POUTHL
Figure 10-13 Timer Timing
10.11 Quadrature Decoder Timing
Table 10-21 Quadrature Decoder Timing1, 2
Operating Conditions: VSS = VSSA_ADC = 0V, VDD_IO = VDDA_ADC = 3.0-3.6V, TA = -40 to +125C, CL 50pF Characteristic Quadrature input period Quadrature input high/low period Quadrature phase period Symbol PIN PHL PPH Min 4T + 12 2T + 6 1T + 3 Max -- -- -- Unit ns ns ns See Figure 10-14 10-14 10-14
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns. 2. Parameters listed are guaranteed by design.
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Serial Communication Interface (SCI) Timing
PPH
PPH
PPH
PPH
Phase A (Input)
PHL PIN PHL
Phase B (Input)
PHL PIN PHL
Figure 10-14 Quadrature Decoder Timing
10.12 Serial Communication Interface (SCI) Timing
Table 10-22 SCI Timing1
Operating Conditions: VSS = VSSA_ADC = 0V, VDD_IO = VDDA_ADC = 3.0-3.6V, TA = -40 to +125C, CL 50pF Characteristic Baud Rate2 RXD3 Pulse Width TXD4 Pulse Width Symbol BR RXDPW TXDPW Min Max (fMAX/16) 1.04/BR 1.04/BR Unit Mbps ns ns See Figure
--
0.965/BR 0.965/BR
--
10-15 10-16
1. Parameters listed are guaranteed by design. 2. fMAX is the frequency of operation of the system clock in MHz, which is 60MHz for the 56F8322 device. 3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
RXD SCI receive data pin (Input)
RXDPW
Figure 10-15 RXD Pulse Width
TXD SCI receive data pin (Input)
TXDPW
Figure 10-16 TXD Pulse Width
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10.13 Controller Area Network (CAN) Timing
Table 10-23 CAN Timing1
Operating Conditions: VSS = VSSA_ADC = 0V, VDD_IO = VDDA_ADC = 3.0-3.6V, TA = -40 to +125C, CL 50pF, fop = 60MHz Characteristic Baud Rate Bus Wakeup detection Symbol BRCAN T WAKEUP Min Max 1 Unit Mbps s See Figure
--
TIPBUS
--
10-17
--
1. Parameters listed are guaranteed by design
MSCAN_RX CAN receive data pin (Input)
T WAKEUP
Figure 10-17 Bus Wakeup Detection
10.14 JTAG Timing
Table 10-24 JTAG Timing
Characteristic TCK frequency of operation1 TCK clock pulse width TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time Symbol fOP tPW tDS tDH tDV tTS tTRST tDE Min DC 50 5 5 -- -- 2T2 2T Max SYS_CLK/8 -- -- -- 30 30 -- -- Unit MHz ns ns ns ns ns ns ns See Figure 10-18 10-18 10-19 10-19 10-19 10-19 10-20 10-21
1. TCK frequency of operation must be less than 1/8 the processor rate. 2. T = processor clock period (nominally 1/60MHz)
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JTAG Timing
1/fOP tPW
VIH
tPW
VM
TCK (Input) VM = VIL + (VIH - VIL)/2
VM VIL
Figure 10-18 Test Clock Input Timing Diagram
TCK (Input)
tDS tDH
TDI TMS (Input) TDO (Output)
Input Data Valid
tDV
Output Data Valid
tTS
TDO (Output)
tDV
TDO (Output)
Output Data Valid
Figure 10-19 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 10-20 TRST Timing Diagram (This pin is always tied inactive on the 56F8322)
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10.15 Analog-to-Digital Converter (ADC) Parameters
Table 10-25 ADC Parameters
Characteristic Input voltages Resolution Integral Non-Linearity 1 Differential Non-Linearity Monotonicity ADC internal clock Conversion range ADC channel power-up time ADC reference circuit power-up time Conversion time Sample time Input capacitance Input injection current3, per pin Input injection current, total VREFH current ADCA current ADCB current Quiescent current Calibrated Gain Error (transfer gain) Calibrated Offset Voltage Uncalibrated Gain Error Uncalibrated Offset Voltage Crosstalk between channels Common Mode Voltage Signal-to-noise ratio Signal-to-noise plus distortion ratio Total Harmonic Distortion Spurious Free Dynamic Range Effective Number Of Bits Vcommon SNR SINAD THD SFDR ENOB fADIC RAD tADPU tVREF tADC tADS CADI IADI IADIT IVREFH IADCA IADCB IADCQ EGAINC VOFFSETC EGAIN VOFFSET -- -- .99 -- -- -- -- -- -- -- -- 0.5 VREFL 5 -- -- -- -- -- -- -- -- -- Symbol VADIN RES INL DNL Min VREFL 12 +/- 1 > -1 Typ -- -- +/- 2.4 +/- 0.7 GUARANTEED -- -- 6 -- 6 1 5 -- -- 1.2 12.5 12.5 0 1 0 .996 to 1.004 +/- 12 -60 (VREFH - VREFLO) / 2 64.6 59.1 60.6 61.1 9.6 5 VREFH 16 25 -- -- -- 3 20 3 -- -- 10 -- -- 1.01 +/- 30 -- -- -- -- -- -- -- MHz V tAIC cycles2 ms tAIC cycles4 tAIC cycles4 pF mA mA mA mA mA mA -- mV -- mV dB V db db db db bit Max VREFH 12 +/- 3.2 < +1 Unit V Bits LSB2 LSB2
1. INL measured from Vin = .1VREFH to Vin = .9VREFH 10% to 90% Input Signal Range 2. ADC clock cycles 3. The current that can be injected or sourced from an unselected ADC signal input without inpacting the performance of the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
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Equivalent Circuit for ADC Inputs
10.16 Equivalent Circuit for ADC Inputs
Figure 10-21 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 closed & S3 open, one input of the sample and hold circuit moves to (VREFH-VREFLO)/2 while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFLO)/2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, VREF and the ADC clock frequency.
Analog Input 3 4
C1 S3 S/H C2 C1 = C2 = 1pF
S1
1
2
(VDDA - VSSA )/ 2
S2
1. 2. 3. 4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time; 1pf
Figure 10-21 Equivalent Circuit for A/D Loading
10.17 Power Consumption
See Section 10.1 for a list of IDD requirements for the 56F8322. This section provides additional detail which can be used to optimize power consumption for a given application. Power consumption is given by the following equation: Total power = A: internal [static component]
+B: internal [state-dependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static]
A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic.
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D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the IO cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero Y-intercept.
Table 10-26 IO Loading Coefficients at 10MHz
Intercept PDU08DGZ_ME PDU04DGZ_ME 2.2 .14 Slope 2.0 .14
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. Table 10-26 provides coefficients for calculating power dissipated in the IO cells as a function of capacitive load. In these cases: TotalPower = ((Intercept + Slope*Cload)*frequency/10MHz) where: * Summation is performed over all output pins with capacitive loads * TotalPower is expressed in mW * Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible.
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56F8322 Technical Data Preliminary
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Package and Pin-Out Information 56F8322
Part 11 Packaging
11.1 Package and Pin-Out Information 56F8322
This section contains package and pin-out information for the 56F8322. This device comes in a 48-pin low-profile quad flat pack (LQFP). Figure 11-1 shows the package outline for the 48-pin LQFP case, Figure 12-1 shows the mechanical parameters for the 48-pin LQFP case, and Table 11-1 lists the pinout for the 48-pin LQFP case.
PHASEA0
TC0 RESET PWMA0 PWMA1 VDD_IO PWMA2 PWMA3 PWMA4 PWMA5 VSS IRQA FAULTA0 13
ORIENTATION MARK
37
PHASEB0
CAN_RX
CAN_TX
VDD_IO
VCAP1
TMS
TDO
TCK
TC1
VSS
TDI
INDEX0 HOME0 VDD_IO
PIN 1
Motorola 56F8322
25
XTAL EXTAL VSS VDDA_ADC VSSA_ADC VREFP VREFMID VREFN ANA6
ANA0
ANA1
ANA2
ANA4
Figure 11-1 Top View, 56F8322 48-Pin LQFP Package
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56F8322 Technical Data Preliminary
SCLK0
MISO0
VCAP2
MOSI0
VDD_IO
ANA5
SS0
VSS
113
Table 11-1 56F8322 48-Pin LQFP Package Identification by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Signal Name TC0 RESET PWMA0 PWMA1 VDD_IO PWMA2 PWMA3 PWMA4 PWMA5 VSS IRQA FAULTA0 Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 Signal Name VSS VDD_IO SS0 MISO0 VCAP2 MOSI0 SCLK0 ANA0 ANA1 ANA2 ANA4 ANA5 Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 Signal Name ANA6 VREFN VREFMID VREFP VSSA_ADC VDDA_ADC VSS EXTAL XTAL VDD_IO HOME0 INDEX0 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 Signal Name PHASEB PHASEA TCK TMS TDI TDO VCAP1 VDD_IO VSS CAN_RX CAN_TX TC1
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Package and Pin-Out Information 56F8322
4X
0.200 AB T-U Z
9 A1
48 37
A
DETAIL Y
P
1
36
T
U V
B1
12 25
AE V1
AE
13
24
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 7 12 REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
Z S1 S
4X
T, U, Z
DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AC
AD
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M
BASE METAL TOP & BOTTOM
R
GAUGE PLANE
N
J C E
F D
0.080
M
AC T-U Z
H
W DETAIL AD AA K
SECTION AE-AE
L
CASE 932-03 ISSUE F DATE 02/23/2000
Figure 11-2 56F8322 48-Pin LQFP Mechanical Information
MOTOROLA 56F8322 Technical Data Preliminary 115
0.250
Part 12 Design Considerations
12.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJ x PD) where: = TA RJ = = PD Ambient temperature for the package (oC) Junction to ambient thermal resistance (oC/W) Power dissipation in the package (W)
The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = RJC = RCA = Package junction to ambient thermal resistance C/W Package junction to case thermal resistance C/W Package case to ambient thermal resistance C/W
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT JT PD
116
= = =
Thermocouple temperature on top of package (oC) Thermal characterization parameter (oC)/W Power dissipation in package (W)
56F8322 Technical Data Preliminary MOTOROLA
Electrical Design Considerations
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
12.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation: * * Provide a low-impedance path from the board power supply to each VDD pin on the hybrid controller, and from the board ground to each VSS (GND) pin The minimum bypass requirement is to place six 0.01-0.1F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerlances. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS Bypass the VDD and VSS layers of the PCB with approximately 100F, preferably with a high-grade capacitor such as a tantalum capacitor Because the hybrid controller output signals have fast rise and fall times, PCB trace lengths should be minimal Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. Take special care to minimize noise levels on the VREF, VDDA and VSSA pins Because the Flash memory is programmed through the JTAG/EOnCE port, designers should provide an interface to this port to allow in-circuit Flash programming
56F8322 Technical Data Preliminary 117
* * * * *
* *
MOTOROLA
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1 illustrates the general power control incorporated in the 56F8322. This chip contains an internal regulator which can be disabled The regulator takes regulated 3.3V power from the VDD_IO pins and provides 2.5V to the internal logic of the chip. This means the entire part can be powered from the 3.3V supply. Notes: * * Flash, RAM and internal logic are powered from the core regulator output All circuitry, analog and digital, share a common VSS bus
VDDA_OSC_PLL VDD VCAP I/O CORE ROSC VSS VSSA_ADC ADC VDDA_ADC VREFH VREFP VREFMID VREFN VREFLO
OCS
REG
REG
Figure 12-1 56F8322 Power Management
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Power Distribution and I/O Ring Implementation
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts.
Table 13-1 56F8322 Ordering Information
Part
MC56F8322 MC56F8322
Supply Voltage
3.0-3.6 V 3.0-3.6 V
Package Type
Low-Profile Quad Flat Pack (LQFP) Low-Profile Quad Flat Pack (LQFP)
Pin Count
48 48
Frequency (MHz)
60 60
Temperature Range
-40 to + 105 C -40 to + 125 C
Order Number
MC56F8322VFA60 MC56F8322MFA60
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HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. This product incorporates SuperFlash(R) technology licensed from SST. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003
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